Patents by Inventor David C. Estrada
David C. Estrada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210223979Abstract: On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.Type: ApplicationFiled: March 16, 2021Publication date: July 22, 2021Inventors: Peng LI, Sanjeev N. TRIKA, David C. ESTRADA
-
Publication number: 20190157776Abstract: A pass-through cable connector assembly includes a connector body extending along an axis and having a peripheral wall which surrounds the axis and defines an interior of the connector body, the connector body also having a compartment wall which divides the interior into first and second compartment, the compartment wall having an aperture extending therethrough from the first compartment to the second compartment, the aperture defining an aperture wall. A first cable is located within the first compartment. A first terminal in electrical communication with the first cable is located within the aperture and circumferentially contacts the aperture wall. A second cable in electrical communication with the second cable is located within the second compartment. The first terminal and the second terminal have complementary mating features which mechanically lock the first terminal to the second terminal and place the first terminal in electrical communication with the second terminal.Type: ApplicationFiled: November 22, 2017Publication date: May 23, 2019Inventors: Jesus J. Castillo, Alma L. Leanos, Flavio M. Ono, David C. Estrada
-
Patent number: 10002002Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.Type: GrantFiled: March 21, 2016Date of Patent: June 19, 2018Assignee: INTEL CORPORATIONInventors: David C. Estrada, Vincent J. Zimmer, Palsamy Sakthikumar
-
Publication number: 20160371098Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.Type: ApplicationFiled: March 21, 2016Publication date: December 22, 2016Applicant: INTEL CORPORATIONInventors: DAVID C. ESTRADA, VINCENT J. ZIMMER, PALSAMY SAKTHIKUMAR
-
Patent number: 9411601Abstract: The present disclosure is directed to flexible bootstrap code architecture. A device may comprise equipment for operating the device and an operating system (OS) for operating the equipment. A boot module may also be included in the device to execute boot operations. At least one flexible boot (FB) module in the boot module may interact with the equipment and/or OS during the boot operations to cause the boot operations to become device-specific. An example boot module may comprise a plurality of FB modules. An example FB module may verify a device/chipset identification and may control the boot operations based on the identification. Other example FB modules may select resources to load based on an OS type, may provide a boot configuration table location for use in OS runtime boot configuration or may load variables from a preload variable directory for use in configuring boot operations.Type: GrantFiled: October 29, 2013Date of Patent: August 9, 2016Assignee: Intel CorporationInventors: Vincent J. Zimmer, H. P. Anvin, Michael A. Rothman, David C. Estrada, Nicholas J. Yoke, Gopinatth Selvaraje
-
Patent number: 9292463Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.Type: GrantFiled: September 26, 2012Date of Patent: March 22, 2016Assignee: INTEL CORPORATIONInventors: David C. Estrada, Vincent J. Zimmer, Palsamy Sakthikumar
-
Publication number: 20150121055Abstract: The present disclosure is directed to flexible bootstrap code architecture. A device may comprise equipment for operating the device and an operating system (OS) for operating the equipment A boor, module may also be included in the device to execute boot operations. At least one flexible boot (FB) module in the boot module may interact with the equipment and/or OS during the boot operations to cause the boot operations to become device-specific. An example boot module may comprise a plurality of FB modules. An example FB module may verify a device/chipset identification and may control the boot operations based on the identification. Other example FB modules may select resources to load based on an OS type, may provide a boot configuration table location for use in OS runtime boot configuration or may load variables from a preload variable directory for use in configuring boot operations.Type: ApplicationFiled: October 29, 2013Publication date: April 30, 2015Inventors: Vincent J. Zimmer, H. P. Anvin, Michael A. Rothman, David C. Estrada, Nicholas J. Yoke, Gopinatth Selvaraje
-
Publication number: 20140089551Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.Type: ApplicationFiled: September 26, 2012Publication date: March 27, 2014Inventors: David C. Estrada, Vincent J. Zimmer, Palsamy Sakthikumar
-
Patent number: 7822960Abstract: In some embodiments, the invention involves system and method for resuming from sleep mode using protected storage accessible to an embedded controller. The boot script information is stored in memory that is available only to the embedded controller. Neither the firmware nor OS have access to the boot script. Upon a wake event, the embedded controller either plays the boot script itself, or sends the information to firmware for processing. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2006Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman, David C. Estrada
-
Patent number: 7725747Abstract: Methods of performing power management of a processor are disclosed. One example method includes obtaining a plurality of operating parameters related to the processor, determining potential power states by fitting a curve to the plurality of operating parameters, and selecting at least some of the potential power states as power states used to manage power consumption by the processor. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2006Date of Patent: May 25, 2010Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman, David C. Estrada
-
Publication number: 20080155247Abstract: In some embodiments, the invention involves system and method for resuming from sleep mode using protected storage accessible to an embedded controller. The boot script information is stored in memory that is available only to the embedded controller. Neither the firmware nor OS have access to the boot script. Upon a wake event, the embedded controller either plays the boot script itself, or sends the information to firmware for processing. Other embodiments are described and claimed.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Inventors: Vincent J. Zimmer, Michael A. Rothman, David C. Estrada
-
Patent number: 7293184Abstract: A plurality of instructions corresponding to a power management event are received. An instruction of the plurality of instructions is executed in a first programming system with a first interface, in response to determining that the instruction is in accordance with the first interface. The instruction is executed in a second programming system with a second interface, in response to determining that the instruction is not in accordance with the first interface.Type: GrantFiled: March 30, 2005Date of Patent: November 6, 2007Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman, David C. Estrada, Andrew J. Fish