Patents by Inventor David C. Guiling

David C. Guiling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes
    Patent number: 8110414
    Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Marshall O. Cathey, Jr., Pushpa Mahalingam, Weidong Tian, David C. Guiling, Xinfen Chen, Binghua Hu, Sopa Chevacharoenkul
  • SELECTIVE PLASMA ETCH OF TOP ELECTRODES FOR METAL-INSULATOR-METAL (MIM) CAPACITORS
    Publication number: 20100276783
    Abstract: A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ?100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Applicant: TEXAS INSTRUMENTS INC
    Inventors: MARSHALL O. CATHEY, PUSHPA MAHALINGAM, WEIDONG TIAN, DAVID C. GUILING, XINFEN CHEN, BINGHUA HU, SOPA CHEVACHAROENKUL
  • ON-CHIP ISOLATION CAPACITORS, CIRCUITS THEREFROM, AND METHODS FOR FORMING THE SAME
    Publication number: 20080277761
    Abstract: An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the dielectric stack. The dielectric stack comprises at least one layer of silicon dioxide and at least one layer of silicon nitride, wherein the layer of silicon nitride is located immediately below or immediately above the top plate.
    Type: Application
    Filed: January 30, 2008
    Publication date: November 13, 2008
    Inventors: Pushpa Mahalingam, David C. Guiling, Sunny K. Lee, Ramon F. Figueroa, Weidong Tian, Yvonne D. Patton, Imran M. Khan