Abstract: A superconductor device includes a high superconductivity transition temperature enhanced from the raw material transition temperature. The superconductor device includes a matrix material and a core material. The enhancing matrix material and the core material together create a system of strongly coupled carriers. A plurality of low-dimensional conductive features can be embedded in the matrix. The low-dimensional conductive features (e.g., nanowires or nanoparticles) can be conductors or superconductors. An interaction between electrons of the low-dimensional conductive features and the enhancing matrix material can promote excitations that increase a superconductivity transition temperature of the superconductor device.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Abstract: A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Abstract: Input is received that selects an animation aspect associated with an object within an animation. The animation involves the object and an original frame of reference through which the animation is displayed, and the selected animation aspect is one that changes over time with respect to the original frame of reference. The animation is displayed through a new frame of reference defined by holding the selected animation aspect constant over time. During the animation display through the new frame of reference, input is received that manipulates the object to create a new animation aspect associated with the object. The new animation aspect associated with the object is recorded in the animation.

Abstract: A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

Abstract: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: A voltage indicating device comprises a test port disposed in a casing that allows the test port to operate during extreme conditions, such as corrosive or explosive environments. The indicating device is coupled to a housing enclosing an electrical apparatus and is connected to a power source of the electrical apparatus. The test port is accessible outside the housing and allows a user to determine voltage or current presence prior to opening the housing, thus preventing electrocution.

Abstract: A system provides processes image data by obtaining a first image in a first data format such as a raster image. The system applies a tracing algorithm to the first image to produce a trace image of the first image. The trace image is maintained in a second data format such as a vector data format. The system displays, in an overlapping format, each of the first image in the first data format and the trace image in the second data format to allow the used to compare the differences between the two image formats. The system also provides a live trace feature that automatically applies changes to the first image in the first data format to the trace image.

Abstract: A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.

Abstract: A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Abstract: The present invention serves to prevent severe injury, loss of life or damage to expensive equipment by creating a system in which the conductors of a plug and the conductors of a receptacle can only be arranged, one with respect to the other, in a unique rotational manner depending upon the intended electrical rating of the plug and receptacle. The resulting plug will mate only with a receptacle having that same configuration. A separate indexer is disposed between the plug body and the conductor assembly to the conductors in the plug to prevent entry of the plug into a differently indexed receptacle. A polarizer in the receptacle fixes the conductor assembly of the receptacle in the same manner as the plug, to allow the plug and receptacle to be mated together when the receptacle is wired for the same electrical rating as the equipment to be energized by the plug.