Abstract: A system, method and computer program product to synchronize processing across multiple lanes. In a system, a synchronizing interface network controller (SINC) communicates with a plurality of processors. Each processor executes an application having thread(s) of operation. Each processor notifies the SINC when a specific thread is ready to perform a respective operation. The SINC releases the processors to perform the respective operation upon being notified by all processors that the specific thread is ready to perform the respective operation. Each processor is configured to monitor for the release of the processors and to also determine whether sufficient time remains within a time window to perform the respective operation. If insufficient time remains, a processor notifies the SINC that the specific thread is no longer ready to perform the respective operation. If the processors are released by the SINC while sufficient time remains, each processor performs the respective operation.

Abstract: A system, method and computer program product to synchronize processing across multiple lanes. In a system, a synchronizing interface network controller (SINC) communicates with a plurality of processors. Each processor executes an application having thread(s) of operation. Each processor notifies the SINC when a specific thread is ready to perform a respective operation. The SINC releases the processors to perform the respective operation upon being notified by all processors that the specific thread is ready to perform the respective operation. Each processor is configured to monitor for the release of the processors and to also determine whether sufficient time remains within a time window to perform the respective operation. If insufficient time remains, a processor notifies the SINC that the specific thread is no longer ready to perform the respective operation. If the processors are released by the SINC while sufficient time remains, each processor performs the respective operation.

Abstract: A homomorphic encryption based high integrity computing system including a processing system including a single-string computation channel configured to receive encrypted input data from at least one data source. The processing system includes at least one processor hosting at least one hosted function. The processor is configured to provide high integrity homomorphic encryption-based computations thereon. This enables isolated channel computations within a single physical computation channel. The at least one processor provides encrypted output data, wherein the encrypted output data is configured to enable computational integrity validation by a receiver.

Abstract: A system and method for ensuring a minimum required availability of a Hosted Function (HF) may retain an entirety of a cache content between separate instances of one or more HF which may share a cache resource. Based on controlling a relationship between an unavailability of cache memory desired by the HF to a probability of the available cache being unusable by the HF, each activation period may be variable within a tolerance to achieve a certification strategy. The approach may statistically characterize a best case, expected case, and worst case of cache availability. The system and method may determine a quality of the cache state at the activation of a particular HF and, based on the statistical analysis of that quality over time, determine a desired derated activation period for each HF to achieve a minimum level of computational availability for successful activation of the HF.

Abstract: A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.

Abstract: A method for administering an intermittent source of electrical power generation, such as a wind powered electric power generating facility, to produce electric power at a level up to a pre-set level during a selected time period.

Abstract: A method for administering an intermittent source of electrical power generation, such as a wind powered electric power generating facility, to produce electric power at a level up to a pre-set level during a selected time period.