Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal.

Abstract: An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Abstract: A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.

Abstract: An integrated circuit temperature sensor includes a sensor to determine whether the integrated circuit is currently exposed to a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected if the sensor indicates exposure to the relatively low temperature or, a measured delta voltage across the base-emitter of the bipolar transistor is selected if the sensor indicates exposure to the relatively high temperature. The voltage across the base-emitter is compared against a first reference for determining exposure to a too cold condition or the selected measured delta voltage across the base-emitter is compared against a second reference for determining exposure to a too hot condition. In a test mode, the measured delta voltage across the base-emitter and/or the measured voltage across the base-emitter are scaled.

Abstract: A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Abstract: A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages.

Abstract: A digital-to-analog converter, in response to a digital signal, selectively taps a resistor string to generate an analog output and selectively shunts around resistors in the string to voltage shift the analog output. If two supply voltage sets are present, two strings are provided. A mutually exclusively selection of outputs is made to select a source of the analog output. An integrated circuit temperature sensor uses the converter and includes a sensing circuit that determines exposure to one of a relatively low or high temperature. A measured voltage across the base-emitter of a bipolar transistor is selected in low temperature exposure and compared against a first reference for a too cold temperature condition. Alternatively, a measured delta voltage across the base-emitter is selected in high temperature exposure and compared against a second reference voltage for a too hot temperature condition. Through the comparisons, a temperature exposure detection is made.

Abstract: A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively low temperature or, alternatively, selects a measured delta voltage across the base-emitter of the bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively high temperature. A comparator compares the selected measured voltage against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to a too cold or too hot temperature.

Abstract: A battery protection structure is described. The structure provides battery overcharging protection while allowing for minimal battery voltage drop during normal battery operation. One resistance element sets voltage drop during normal operation, and the sum of two resistance elements sets the maximum battery charging current which will be allowed. The structure provides protection against single component failures.

Abstract: A circuit includes a volatile memory array and a logic circuit operable to detect a memory array tamper situation and generate at least one control signal responsive thereto. Circuitry associated with each of the individual cells within the volatile memory array responds to the at least one control signal by destroying any data stored by the associated memory cell. Data is destroyed using one of several options including: shorting a true node of the latch to a complement node of the latch, shorting the true and complement nodes of the latch to a bit line and a complement bit line, shorting one of the true/complement nodes of the latch to a reference voltage, shorting both the true and complement nodes of the latch to at least one reference voltage, coupling a first and second positive reference voltage inputs to a positive/ground voltage supply, or shorting the bit line to a reference voltage while the pass gate is activated.

Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

Abstract: A regulator circuit and method are disclosed for a system. The regulator circuit may include a compare circuit for comparing a first supply voltage to a predetermined voltage level and generating an enable signal based upon the comparison. A selectively enabled voltage regulator is adapted to make available a predetermined current level at a regulated voltage when enabled by the compare circuit. When disabled, the voltage regulator circuit is prohibited from providing current. The voltage regulator may include an output transistor that is normally biased in a saturation mode of operation and is deactivated by the enable signal. By controlling the output transistor based upon the output of the compare circuit, the need for a relatively large transistor for connecting to the first supply voltage is eliminated.

Abstract: An electronic device incorporates a primary function circuit and a voltage regulator that provides a regulated voltage signal to the primary function circuit. The voltage regulator is responsive to a stress-enable signal indicative of whether or not an external voltage supplied to the voltage detector is within a predetermined range. The output voltage signal is controlled to be at a first voltage level when the external voltage is within the predetermined voltage range and at a second voltage level when the external voltage is outside of the predetermined range. The second voltage level may be an elevated voltage level to facilitate stress testing or burin-in of the electronic device.

Abstract: A method and circuit are disclosed for an integrated circuit having one or more memory cells, each memory cell including first and second p-channel transistor and first and second n-channel transistors configured as cross-coupled logic inverters between first and second reference voltage levels during a normal mode of operation. Power control circuitry is coupled to a source terminal of the first p-channel transistor of each memory cell for providing to the first p-channel transistors the first reference voltage level during the normal mode of operation. This causes a first voltage less than the first reference voltage level to appear at the source terminal of the first p-channel transistors during a data corruption mode of operation wherein data stored in the one or more memory cells is corrupted.