Patents by Inventor David C. Mosher

David C. Mosher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163697
    Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
  • Publication number: 20170207121
    Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
    Type: Application
    Filed: April 4, 2017
    Publication date: July 20, 2017
    Applicant: GlobalFoundries Inc.
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
  • Patent number: 9673091
    Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
  • Publication number: 20160379878
    Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
  • Patent number: 6348419
    Abstract: A method for adjusting an etch rate of a nitride layer, in accordance with the present invention includes, in a reaction chamber, providing a surface for depositing a nitride layer. The nitride layer is deposited on the surface by adjusting processing parameters to control an etch rate achievable for the nitride layer. The etch rate achievable results from the depositing step such that an ability to etch the nitride layer is determined by the adjustment of the process parameters. A refractive index measurement may be provided for monitoring the achievable etch rate for the nitride layer.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: February 19, 2002
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Frank Grellner, Paul C. Jamison, Glen L. Miles, David C. Mosher, Emmanuel Batt