Abstract: A method for failure analysis of small contacts in integrated circuits is provided. A number of opposing electrical contacts is configured to contact a sample in an offset pattern such that any one electrical contact may contact more than one conductor in the sample and any opposing electrical contact is offset-positioned to contact no more than one of the conductors contacted by the one electrical contact.

Abstract: A system and method for wafer level global bitmap characterization include determining chip level defect data bitmaps from a semiconductor wafer, and consolidating the chip level defect data bitmaps into a global wafer level bitmap that characterizes substantially the entire wafer failure configuration. The global wafer level bitmap is then analyzed and compared with other global wafer level bitmaps to develop correlations thereamong and develop global wafer level bitmap definitions for conducting at least one of wafer-to-wafer, boat-to-boat, and lot-to-lot process analysis based upon the global wafer level bitmap definitions.