Abstract: Bus command generation apparatus is provided for a microprocessor implemented data processing system that uses a multibyte width system bus requiring a bus command byte since a complete bus command byte is ordinarily unavailable directly from a microprocessor. A bus command register is loaded with a preliminary bus command, certain bits of which are then modified in accordance with the operation to be performed. The limited command information available from the microprocessor that controls I/O operations is utilized to modify the preliminary bus command bytes without any need to access memory for bus command information. The bus command generation apparatus is adapted to pass a preliminary bus command byte unaltered, under predefined conditions, to the system bus.