Abstract: An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to antenna structures and methods of manufacture. The structure includes an antenna cell comprising a single P-well isolated by a deep trench isolation structure and including at least one diffusion region.

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure including a gate structure over a semiconductor layer. The gate structure includes a first portion having a first horizontal width, and a second portion laterally adjacent the first portion and having a second horizontal width less than the first horizontal width. A gate contact is on the first portion of the gate structure and is not on the second portion of the gate structure.

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.