Patents by Inventor David C. Pritchard

David C. Pritchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11913971
    Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 27, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Romain H. A. Feuillette, David C. Pritchard, Elizabeth Strehlow, James P. Mazza
  • Patent number: 11722298
    Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 8, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Romain H. A. Feuillette, David C. Pritchard, Bernhard J. Wunder, Elizabeth Strehlow
  • Publication number: 20230131403
    Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure including a gate structure over a semiconductor layer. The gate structure includes a first portion having a first horizontal width, and a second portion laterally adjacent the first portion and having a second horizontal width less than the first horizontal width. A gate contact is on the first portion of the gate structure and is not on the second portion of the gate structure.
    Type: Application
    Filed: October 25, 2021
    Publication date: April 27, 2023
    Inventors: David C. Pritchard, Hongru Ren, Zhixing Zhao
  • Publication number: 20220268805
    Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Romain H.A. Feuillette, David C. Pritchard, Elizabeth Strehlow, James P. Mazza
  • Publication number: 20220085994
    Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Romain H. A. Feuillette, David C. Pritchard, Bernhard J. Wunder, Elizabeth Strehlow
  • Patent number: 11239087
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 1, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
  • Patent number: 11226231
    Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: January 18, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob, Yusheng Bian, David C. Pritchard
  • Publication number: 20210404867
    Abstract: An image sensor includes an array of optically switchable magnetic tunnel junctions (MTJs) arranged in columns and rows. The image sensor has first lines of transparent conductive material and second lines of conductive material. Each first line is in contact with the free layers of the MTJs in a corresponding row. Each second line is electrically connected to the fixed layers MTJs in a corresponding column. The first lines are concurrently exposable to radiation. The first and second lines are selectively biasable. In a global reset operation, biasing conditions are such that all MTJs are switched to an anti-parallel state. In a global sense operation, biasing conditions are such that, depending upon the intensity of radiation received at those portions of the first lines in contact with MTJs, the MTJs may switch to a parallel state. In selective read operations, biasing conditions are such that stored data values in the MTJs can be read.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob, Yusheng Bian, David C. Pritchard
  • Patent number: 10691862
    Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Neha Nayyar, Daniel J. Dechene, David C. Pritchard, George J. Kluth
  • Publication number: 20200058515
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Heng YANG, David C. PRITCHARD, George J. KLUTH, Anurag MITTAL, Hongru REN, Manjunatha G. PRABHU, Kai SUN, Neha NAYYAR, Lixia LEI
  • Patent number: 10497576
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
  • Publication number: 20190012422
    Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 10, 2019
    Inventors: Neha NAYYAR, Daniel J. DECHENE, David C. PRITCHARD, George J. KLUTH
  • Patent number: 10068806
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Publication number: 20180182674
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 28, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Publication number: 20180108571
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Patent number: 9947590
    Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
  • Patent number: 7803980
    Abstract: A multi layered wound dressing which comprises an adhesive layer, an absorbent layer overlying said adhesive layer on the surface furthest from the wound, and a moisture transmitting cover layer overlying the absorbent layer, the dressing having a total thickness of less than 1.5 mm.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: September 28, 2010
    Assignee: ConvaTec Technologies Inc.
    Inventors: Bryan Griffiths, David C. Pritchard, Elizabeth Jacques, Steven M. Bishop, Michael Lydon
  • Publication number: 20040236260
    Abstract: A multi layered wound dressing which comprises an adhesive layer, an absorbent layer overlying said adhesive layer on the surface furthest from the wound, and a moisture transmitting cover layer overlying the absorbent layer, the dressing having a total thickness of less than 1.5 mm.
    Type: Application
    Filed: July 1, 2004
    Publication date: November 25, 2004
    Inventors: Bryan Griffiths, David C. Pritchard, Elizabeth Jacques, Steven M. Bishop, Michael J. Lydon
  • Patent number: 6793645
    Abstract: A multi layered wound dressing which comprises an adhesive layer, an absorbent layer overlying said adhesive layer on the surface furthest from the wound, and a moisture transmitting cover layer overlying the absorbent layer, the dressing having a total thickness of less than 1.5 mm.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: September 21, 2004
    Assignee: Bristol-Myers Squibb Company
    Inventors: Bryan Griffiths, David C. Pritchard, Elizabeth Jacques, Steven M. Bishop, Michael J. Lydon
  • Publication number: 20020038099
    Abstract: A multi layered wound dressing which comprises an adhesive layer, an absorbent layer overlying said adhesive layer on the surface furthest from the wound, and a moisture transmitting cover layer overlying the absorbent layer, the dressing having a total thickness of less than 1.5 mm.
    Type: Application
    Filed: July 12, 2001
    Publication date: March 28, 2002
    Inventors: Bryan Griffiths, David C. Pritchard, Elizabeth Jacques, Steven M. Bishop, Michael J. Lydon