Abstract: An article is provided and includes a fleece layer and layers of polysiloxane materials applied as a skin to both sides of the fleece layer.

Abstract: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

Abstract: A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of the time values stored in the memory.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A control system for executing an application program is disclosed herein. The control system includes a plurality of main processor modules. The control system further includes a plurality of input/output modules for providing input process data to associated ones of the plurality of main processor modules. A voting system is operative to compare the input process data associated with first and second of the plurality of main processor modules to the input process data associated with a third of the main processor modules. This results in generation of voted input process data utilized by the third main processor module in executing the application program. In certain implementations the system includes a high-speed bus for distributing the voted input process data to the first and second main processor modules, each of which also executes the application program based upon the voted input process data.

Abstract: A measurement system and method for determining a revolution rate of a rotating gear is described. Such a rotating gear can be, for example, a turbine or compressor. The described measurement system and method, for example, can perform highly accurate measurements and can be a fault tolerant system providing high reliability. In one embodiment, an apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: An apparatus comprises an edge detector, a memory and a pulse-input engine. The edge detector is configured to receive an input signal and a counter signal. The edge detector is further configured to send a set of time values based on the input signal and the counter signal. Each time value from the set of time values is uniquely associated with a detected edge transition from the input signal. The memory is coupled to the edge detector. The memory is configured to receive from the edge detector the set of time values. The memory is configured to store the set of time values. The pulse-input engine is coupled to the memory. The pulse-input engine is configured to measure a set of pulse-to-pulse delays based on the set of time values stored in the memory.

Abstract: A control system for executing an application program is disclosed herein. The control system includes a plurality of main processor modules. The control system further includes a plurality of input/output modules for providing input process data to associated ones of the plurality of main processor modules. A voting system is operative to compare the input process data associated with first and second of the plurality of main processor modules to the input process data associated with a third of the main processor modules. This results in generation of voted input process data utilized by the third main processor module in executing the application program. In certain implementations the system includes a high-speed bus for distributing the voted input process data to the first and second main processor modules, each of which also executes the application program based upon the voted input process data.

Abstract: A controller for executing an application program to process control information related to control elements includes one or more main processors that each run the application program; a time synchronization system that synchronizes the time clocks of the main processors; and a voting system that exchanges information between the main processors and compares the information received from the other main processors. In addition, the controller includes one or more rendezvous signals sent to and received by the main processors as well as a mechanism for updating the time clocks based on a clocking midpoint of all processor signals.