Abstract: The present invention comprises a user-programmable control circuit for use in a power converter to automatically transition the converter into BURST mode when load current demand is low. The control circuit senses load current demand by monitoring the output current of the converter, and generating a signal representative of the monitored output current. The control circuit may automatically transition the converter into BURST mode when the signal indicative of the average monitored output current decreases below a user-programmable threshold. BURST mode may increase overall converter efficiency by turning OFF a plurality of electronic components, and maintaining the converter's output voltage at a regulated level by energy stored in an output capacitor.

Abstract: A boost regulator circuit is designed to maintain nearly constant intensity from a flashlight lamp, compensating for the drop in battery voltage over an operating lifetime. The quality of the light output is improved, and battery life is extended. An asynchronous boost regulator circuit and two synchronous boost regulator circuits are shown. The regulator circuit begins boosting after battery voltage has fallen by 15-20%, and maintains output voltage at a substantially constant level until a major portion of the stored battery energy has been consumed. A circuit assembly is shown that can be used to retrofit existing flashlights. The circuit assembly resides on a disk-shaped circuit board that can be placed between the lamp and an adjacent battery. Contacts formed on the circuit board provide connections to the battery, the lamp, and to a common connection point such as ground.

Abstract: A transformer isolates a control circuit from a FET, the control circuit including a clock generator for providing, when enabled, a clock signal to the transformer primary. A PWM input selectively disables the clock generator from providing the clock signal to the transformer primary. The transformer secondary is connected in a full wave centertap configuration for providing a full wave rectified version of the clock signal, the full wave rectified version being a relatively constant DC voltage signal supplied at one level to the FET to turn on the FET when the clock generator is enabled to provide the clock signal to the primary. The centertap configuration provides a relatively constant DC voltage signal at a second level to the FET to turn off the FET when the clock generator is disabled by the PWM input from providing the clock signal to the primary.

Abstract: A resettable current limiter is started using an externally generated reset signal, latches on and continues conducting until an overload current is sensed, at which time the limiter shuts off load current. An FET is used both as a series pass element anda load current sensing element. A comparator senses the source of drain voltage drop across the FET and provides a shutdown signal to the FET's gate upon sensing an overload. The limiter may also comprise a solid state switch for positively shutting off the FET using an externally generated off signal. The reset signal reponse circuitry may be set up to be edge triggered to protect against an external short. The reset signal may be a level change or may be a periodic signal. A zener diode may be used for both protecting the FET against excessive voltages and against current surges.