Abstract: A main memory unit for a data processing system has at least one memory board and allows each memory board to process data simultaneously. Each memory board may also include a plurality of memory array units which also can process data simultaneously. The main memory unit includes a memory interface unit, at least one memory board, and a memory unit bus for transferring address, data, command, and memory status signals between the memory boards and the memory interface unit.

Abstract: For use in a data processing system, a main memory subsystem includes a plurality of memory boards for storing groups of logic signals. Each memory board includes an plurality of array units. Each array unit is adapted to store a group of logic signals that is equivalent in size to the field of data logic signals transferred on the system bus and has an address structure so that each addressable data signal group can be stored in a single array. The address field of each array unit is further adapted so that the probability of interfering activity in each array is low. The arrays are adapted process data signal groups independently, thus, activity involving several arrays can take place simultaneously. The memory subsystem is structured to provide a pipeline types of overlapping activity so that activity involving several array units can be in progress simultaneously.

Abstract: In a data processing system having a multiple write command and a masked write command, a plurality of signal groups can be transferred from a data processing subsystem to a memory unit on consecutive system cycles. Associated with each signal group and applied to lines used to transfer mask signals are control signals that designate when the associated signal group is to stored in the memory unit. When the multiple write command is issued, the apparatus coupled to the mask signal lines is enabled and the control signals can be identified. When the control signals are identified, the operation storing the associated signal group is inhibited.

Abstract: Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.