Patents by Inventor David C. Sing

David C. Sing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938065
    Abstract: A surgical patient support includes a foundation frame, a support top, and a brake system. The foundation frame includes a first column and a second column. The support top is coupled to the first column and the second column for rotation about a top axis extending along the length of the support top. A single-handle unlock for the support top is also provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 26, 2024
    Assignee: Allen Medical Systems, Inc.
    Inventors: Joshua C. Hight, David P. Scott, Thomas K. Skripps, Orlando Soto, Darwin Keith-Lucas, Justin I. McCarthy, Jack B. Sing, Jeffrey C. Marrion, Phillip B. Dolliver, Joshua J. Moriarty
  • Patent number: 8258035
    Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 4, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
  • Patent number: 7648884
    Abstract: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: January 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Byoung W. Min, James K. Schaeffer, David C. Sing
  • Publication number: 20080274600
    Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
    Type: Application
    Filed: May 4, 2007
    Publication date: November 6, 2008
    Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
  • Publication number: 20080206939
    Abstract: A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.
    Type: Application
    Filed: February 28, 2007
    Publication date: August 28, 2008
    Inventors: Byoung W. Min, James K. Schaeffer, David C. Sing
  • Publication number: 20080173957
    Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
    Type: Application
    Filed: August 31, 2007
    Publication date: July 24, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Venkat R. Kolagunta, David C. Sing
  • Patent number: 7323373
    Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: January 29, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, David C. Sing, Venkat Kolagunta
  • Patent number: 7282426
    Abstract: A method for forming a semiconductor device including forming a semiconductor substrate; forming a gate electrode over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area under the gate electrode and adjacent the first side of the gate electrode, a second area under the gate electrode and adjacent the second side of the gate electrode, and a third area under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Venkat R. Kolagunta, David C. Sing
  • Publication number: 20030160233
    Abstract: Predetermined regions of a transistor are activated using a buried energy absorbing layer. The buried energy absorbing layer is under a semiconductor layer, in which a transistor is being formed. Amorphous regions are formed within the semiconductor layer on either side of a control electrode and a gate dielectric. An energy source with a wavelength that is not absorbed by the amorphous regions or the control electrode is applied to the transistor and absorbed by the energy absorbing layer. The energy absorbing layer transfers the energy into heat, which is at a temperature greater than or equal to the melting temperature of the amorphous regions and less than the melting temperature of the semiconductor layer. Due to the heat, the amorphous regions melt and recrystallize, thereby becoming electrically active. However, the control electrode does not melt.
    Type: Application
    Filed: February 28, 2002
    Publication date: August 28, 2003
    Inventors: Michael J. Rendon, William J. Taylor, David C. Sing