Abstract: A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can float with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrapping capacitor can be used to charge the synchronous bootstrapping capacitor of another (higher level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply Vdd.

Abstract: A gate driver for a power switch, comprising a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch; a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; and a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch.

Abstract: A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a system controller. Power switches in both a power converter and power inverter are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller. The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive. A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: A motor drive system control provides global closed loop feedback to cooperatively operate system components to adaptively reduce noise and provide noise cancellation feedback. An active EMI filter reduces differential and common mode noise on an input and provides a noise level indication to a system controller. Power switches in both a power converter and power inverter are cooperatively controlled with dynamic dv/dt control to reduce switching noise according to a profile specified by the controller. The dv/dt control is provided as an analog signal to a high voltage IC and codified as a pulse width for a level shifting circuit supplying control signals to the high voltage gate drive. A noise extraction circuit and technique obtain fast noise sampling to permit noise cancellation and adaptive noise reduction.

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Abstract: Circuits for communicating between high side devices and low side controllers without using level shifting switches are provided. A low voltage controller with time coding circuitry generates an output, such as a voltage, a current, or a digital signal for controlling a high side switch. A driver is connected to the high side switch and receives the signal from the controller, decodes the signal, and generates on and off time pulses for controlling the high side switch. The communication between the controller and the driver does not require any level shifting circuitry.

Abstract: Circuits for communicating between high side devices and low side controllers without using level shifting switches are provided. A low voltage controller with time coding circuitry generates an output, such as a voltage, a current, or a digital signal for controlling a high side switch. A driver is connected to the high side switch and receives the signal from the controller, decodes the signal, and generates on and off time pulses for controlling the high side switch. The communication between the controller and the driver does not require any level shifting circuitry.

Abstract: A circuit for recovering a signal of interest which is offset by a common mode displacement, such is the case when the signal is the voltage across a current sense resistor located on the high side bus or between the switches of a motor controller circuit. The circuit of the present invention converts the voltage across the resistor into a pulse code modulated data, then downshifts the voltage, and then recovers the signal of interest at the lower voltage by demodulating the signal. The recovered signal is then processed, either with a synchronized sample and hold circuit to provide an analog output, or with a counter and latch to provide a digital output.

Abstract: A method and circuit for driving power transistors arranged in series in a half bridge configuration allowing for excessive negative swing of an output node between the transistors in the half bridge configuration. The series transistors are connected between a first voltage source and a common potential. A second voltage reference source is also provided. A terminal is connected to a common point coupled to anodes of intrinsic diodes of driver circuits for the power transistors. The second voltage source is connected between the common potential and the terminal so as to shift the level of the common point such that the intrinsic diodes will not forward bias due to negative output node transients generated by diode forward recovery and stray inductances. The circuit of the invention can also be incorporated in an integrated circuit including a single chip, e.g., a silicon chip.

Abstract: The logic circuit of the level shifting circuit of a high side MOS gate device is made reset dominant to make the circuit immune to noise glitches. The reset dominance is obtained by causing a reset signal to be produced at a wider range of high side floating supply offset voltage than that at which the set signal can be produced to prevent the chance of a set when the high side power MOSFET should be off. The reset dominance is obtained by increasing the size of the reset voltage dropping resistor or by adjusting the input threshold of the circuit reading the set and reset voltage dropping resistors.

Abstract: A circuit for driving power transistors in a half bridge configuration from a control signal referenced to any potential between the line voltage for the power transistors and the line voltage return.

Abstract: A multi-layered neural network is disclosed that converts an incoming temporally coded spike train into a spatially distributed topographical map from which interspike-interval and bandwidth information may be extracted. This neural network may be used to decode multiplexed pulse-coded signals embedded serially in an incoming spike train into parallel distributed topographically mapped channels. A signal processing and code conversion algorithm not requiring learning is provided.