Abstract: A system and method are provided for performing 32-bit or dual 16-bit floating-point arithmetic operations using logic circuitry. An operating mode that specifies an operating mode for a multiplication operation is received, where the operating mode is one of a 32-bit floating-point mode and a dual 16-bit floating-point mode. Based on the operating mode, nine recoding terms for a mantissa of at least one floating-point input operand are determined. A dual-mode multiplier array circuit that is configurable to generate partial products for either one 32-bit floating-point result or for two 16-bit floating-point results computes the partial products based on the nine recoding terms. The partial products are processed to generate an output based on the operating mode.

Abstract: A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output.

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract: A method for applying texture mapping in per-pixel operations includes receiving a plurality of parameters. The parameters define a pixel value at a pixel in a graphics primitive. From among these parameters, a set of parameters is selected to be associated with textures. The parameters that are not selected define a set of unselected parameters that have constant values over the primitive. A texture value is then determined for each of the selected parameters by accessing a set of textures, with the texture value for the selected parameters varying over the primitive. The pixel value at the pixel is then evaluated using the constant unselected parameters and the texture values for the selected parameters. A device and system for applying texture mapping in per-pixel operations also are described.

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract: Systems and methods for delivering two data streams via two buses allow one of the buses to be used for delivering selected elements of the data stream that is primarily being delivered by the other bus. At an input rerouting circuit, the selected elements are rerouted from the second data stream into the first data stream; a token inserted in the second data stream identifies a position of the rerouted element. The modified streams are transmitted by the two buses. A receiving circuit reinserts the rerouted data element into the second data stream at the sequential position identified by the placeholder token.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Abstract: A graphics processing subsystem includes a vertex processing unit that allows vertex shader programs to arbitrarily access data stored in vertex texture maps. The vertex processing unit includes a vertex texture fetch unit and vertex processing engines. The vertex processing engines operate in parallel to execute vertex shader programs that specify operations to be performed on vertices. In response to a vertex texture load instruction, a vertex processing engine dispatches a vertex texture request to the vertex texture fetch unit. The vertex texture fetch unit retrieves the corresponding vertex texture map data. While the vertex texture fetch unit is processing a vertex texture request, the requesting vertex processing engine is adapted to evaluate whether instructions that follow the vertex texture load instruction are dependent on the vertex texture map data, and if the instructions are not dependent on the vertex texture map data, to execute the additional instructions.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within a numerical range limit of the VPC unit. This limitation reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit can cull many primitives despite its culling limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with culling information previously computed for the vertices. To minimize memory bandwidth, the VPC unit retrieves vertex data used for culling operations first. After completing the culling operations, the VPC unit retrieves the attributes of a vertex only if the primitive has not been culled. The VPC unit applies a perspective correction factor to the vertex attributes.

Abstract: A dual mode device and method is provided for generating cross product or dot product from a pair of vectors. The dual mode device generates a cross product or a dot product from a first vector and a second vector. The first vector has a first set of components and the second vector has a second set of components. The device includes a dual mode controller and a dual mode unit. The dual mode controller receives the first and second vectors and is configured to select vector components for evaluating a cross product component or a dot product in response to a first signal. The first signal indicates whether to generate a cross product component or a dot product. The dual mode unit is coupled to receive the selected vector components and generates the cross product component or the dot product in response to the first signal.

Abstract: A system, method and computer program product are provided for branching during programmable processing in a computer graphics pipeline. Initially, data is received. Programmable operations are then performed on the data in order to generate output. Such operations are programmable by a user utilizing instructions from a predetermined instruction set. When performing the programmable operations in the foregoing manner, programmable branching may take place between the programmable operations. Subsequently, the output is stored in memory. Also included is a system, method and computer program product for directly executing a function in the computer graphics pipeline. Initially, input data is received in the computer graphics pipeline. A mathematical function is directly performed on the input data in order to generate output data. It should be noted that the mathematical function is directly performed in the computer graphics pipeline without a texture look-up or aid from a central processing unit.

Abstract: A graphics subsystem having a programmable shader controllable by both state-based control information, such as DirectX 8 control information, and program instructions, such as DirectX 9 shader program instructions. The programmable shader translates state-based control information received from a host computer into native control information. The programmable shader translates into native control information program instructions fetched from memory locations identified by a received memory reference and program instructions received from the graphics subsystem. Native control information configures computation units of the programmable shader. The programmable shader optimizes the generated native control information by combining certain operations. The graphics subsystem detects memory references sent from the host computer and pre-fetches program instructions for transmission to the programmable shader.

Abstract: A graphics subsystem having a programmable shader controllable by both state-based control information, such as DirectX 8 control information, and program instructions, such as DirectX 9 shader program instructions. The programmable shader translates state-based control information received from a host computer into native control information. The programmable shader translates into native control information program instructions fetched from memory locations identified by a received memory reference and program instructions received from the graphics subsystem. Native control information configures computation units of the programmable shader. The programmable shader optimizes the generated native control information by combining certain operations. The graphics subsystem detects memory references sent from the host computer and pre-fetches program instructions for transmission to the programmable shader.

Abstract: A method and device for associating a pixel on a surface with one of a plurality of regions defined on the surface. The regions are concentric and defined on the surface by a cutoff angle &phgr; and a transition angle &Dgr;. The concentric regions have a center point that is aligned with a source point disposed above the center point. The source point and the center point form a first axis and the source point and the pixel define a second axis between the source point and the pixel. The method and device determine a difference angle (&phgr;−&Dgr;). The difference angle is then converted into cosine space by determining cos(&phgr;−&Dgr;). Next, the difference angle in the cosine space is converted into a log space. The pixel angle &thgr; between the first axis and the second axis is evaluated in the log and cosine spaces. The region in which the pixel belongs is determined by comparing the difference angle and the pixel angle in one or both of the log space and the cosine space.

Abstract: A system and method for determining and applying the effect of light polarization on the rendering of graphics objects. A polarization state buffer is provided to maintain polarization state on a pixel by pixel basis for each pixel in a frame buffer. As graphics objects are rendered the polarization state information is updated based on the underlying opaque surface, the polarization state of the light, and the characteristics of non-opaque objects being drawn. Pixel intensity is adjusted based on the degree of polarization, and the angle of the polarization axis. An approximation of the pixel intensity function is implemented using standard hardware logic.

Abstract: Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.

Abstract: A method and apparatus for the management of the data associated with multiple graphics contexts in a computer graphics rendering system. Graphics contexts are built by graphics engines and selectively saved into a context save RAM. Context switches are managed either by modifying a context base pointer to address a new section of the context save RAM, or by writing out a portion of the context save RAM to external storage and reading in a replacement context from external storage. The writing and reading process are managed by a control processor allowing the graphics engines to switch context at the same time. New contexts read from external storage automatically cause regeneration of downstream rasterization parameters.

Abstract: A multiple-pass system for determining the primitives that are visible in a predetermined pick aperture for a "visible pick" operation. On the first pass, the primitives contained within the pick aperture and thus potentially visible are selected, and each selected primitive is assigned a pick index as an identifier. On the second pass, the pick indices of the selected primitives are rendered to a temporary frame buffer area, using a Z-buffer for hidden surface removal so that only the pick indices of the primitives visible within the pick aperture are stored in the corresponding frame buffer portion. On the third pass, the frame buffer portion corresponding to the pick aperture is read to determine the pick indices of the visible primitives. This information is then used to report back to the host the picked primitives.

Abstract: An implementation of a flexible memory controller for a graphics hardware system that supports flexible allocation of frame buffer resources. The buffer selection and steering to the channels of the modification logic are performed by a programmable controller. Furthermore, the controller is capable of performing pixel functions that require multiple frame buffer accesses per pixel. Still further, independent control is provided for read and write sequences. Also, separate control is provided for buffer selection and bus steering. This function is useful for controlling systems where the frame buffer resources are limited. The present invention allows for assigning various buffers alternate functions based on the application's requirements, and may vary on a per window basis.

Abstract: A method and system for processing a graphics data stream in a computer graphics system having a parallel processing system. The graphics data stream includes a plurality of elements. The method and system of the present invention involve associating tags with elements in a graphics data stream, wherein each tag indicates a display order for the element associated with the tag. The elements are processed within a parallel processing system to produce processed elements, wherein each of the processed elements maintains an association with a tag. The processed elements are rasterized in a selected sequence to determine new pixel data sets, wherein rasterization of each processed element results in a new pixel data set for each of a plurality of pixels. Each new pixel data set includes order data derived from a tag associated with each of the processed elements.