Abstract: A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions.

Abstract: A major/minor loop bubble memory configuration that provides gap free serial access to the data in the minor loops and which maintains the non-volatility of data when subjected to a power-on-off-on sequence. The configuration includes a timing minor loop in combination with the data storage minor loops in the major/minor loop array. The placement of a single timing bubble within the timing loop permits gap free serial access to the data in the remaining storage minor loops.

Abstract: A random access bubble memory directs a plurality of continuous streams of bubbles toward a plurality of storage loops. A write decoder selects one continuous stream of bubbles. An annihilator then transforms this one continuous stream of bubbles into the desired data pattern which is then stored in a selected loop. While the data pattern is being formed, a read decoder directs the data which had been stored in the selected loop to a bubble detector. This memory has a unified read/write cycle which permits intermixed read and write, read/modify/write, and swap operations. This bubble memory allows a user to remove power abruptly during a read/write cycle without returning a partially processed block to its storage loop and without saving the identity of the block. In a preferred embodiment, the read and write decoders are operated simultaneously by identical control currents.

Abstract: A conventional word organized random access memory is modified for image processing operations so that the pq image points of any 1 .times. pq, pq .times. 1 or pxq subarray of an rp .times. sq or smaller image array stored in the memory can be extracted or updated in a single memory cycle. The invention contemplates 2 pq memory modules labeled from 0 to 2pq-1 for storing the image points, each module being capable of storing rs/2 points in distinguishable cells, only one cell of which is randomly accessible in a single instant of time. The invention further contemplates accessing circuitry for causing each image point I(i,j) of an image array to be routed to or from a memory module M(i,j) according to the relation M(i,j)=pq[(i/p)//2]+ (iq+i/2p+j)//pq, where the notations "/" and "//" denote, respectively, the quotient and the remainder resulting from integer division.