Abstract: A power supply may include a power converter circuit may be configured to control a magnitude of an output voltage, and generate a signal indicative of the magnitude of the output voltage. The power supply may include an over-power protection circuit that is configured to receive a feedback signal indicative of a magnitude of an input current of the power converter circuit. The power supply may include a control circuit that is configured to determine a magnitude of a requested power based on the signal indicative of the magnitude of the output voltage, and disable the power supply (e.g., control the magnitude of the output voltage to be zero volts) when the magnitude of the requested power is greater than a second threshold and the magnitude of input power indicated by the first feedback signal is less than a third threshold.

Abstract: A power supply may include a power converter circuit may be configured to control a magnitude of an output voltage, and generate a signal indicative of the magnitude of the output voltage. The power supply may include an over-power protection circuit that is configured to receive a feedback signal indicative of a magnitude of an input current of the power converter circuit. The power supply may include a control circuit that is configured to determine a magnitude of a requested power based on the signal indicative of the magnitude of the output voltage, and disable the power supply (e.g., control the magnitude of the output voltage to be zero volts) when the magnitude of the requested power is greater than a second threshold and the magnitude of input power indicated by the first feedback signal is less than a third threshold.

Abstract: A system may include a plurality of master lighting modules and a fixture controller. The fixture control may include a power converter circuit that is configured to generate a bus voltage on a power bus. The plurality of master lighting modules may be serially-coupled on the power bus. The fixture controller may include a control circuit that is configured to receive an indication of a magnitude of an end bus voltage at an end master lighting module. The end master lighting module may be the master lighting module that is located furthest from the fixture controller along the power bus. The control circuit may be configured to generate a target bus voltage control signal based on the magnitude of the end bus voltage. The power converter circuit may be configured to control a magnitude of the bus voltage based on the target bus voltage control signal.

Abstract: Systems and methods are related to daltonizing images. An image decoder can receive a first image and a second image. The images can be associated with a first metadata and second metadata, respectively. The image decoder and determine a color mapping for the first image and the second image based on the first metadata and the second metadata. The image decoder can process the images in a color vision deficiency (CVD) processor and based on the images and their associated metadata generate daltonized images which are sent to a display.

Abstract: A power supply may include a power converter circuit may be configured to control a magnitude of an output voltage, and generate a signal indicative of the magnitude of the output voltage. The power supply may include an over-power protection circuit that is configured to receive a feedback signal indicative of a magnitude of an input current of the power converter circuit. The power supply may include a control circuit that is configured to determine a magnitude of a requested power based on the signal indicative of the magnitude of the output voltage, and disable the power supply (e.g., control the magnitude of the output voltage to be zero volts) when the magnitude of the requested power is greater than a second threshold and the magnitude of input power indicated by the first feedback signal is less than a third threshold.

Abstract: An adaptive display calibration system includes a display, a photodetector configured to capture light emitted by the display, and a set-top box connected to the display and the photodetector. The set-top box includes processing circuitry configured to transmit one or more test patterns to the display, and receive one or more measurements of the display from the photodetector in response to the test patterns. Additionally, the processing circuitry of the set-top box determines a capability of the display based on the measurements received from the photodetector and programs the set-top box based on the capability of the display.

Abstract: A method and system for allocating pre-selected physical memory locations to an application executing on a data processing system. Memory allocation subroutines, interacting with the programming interfaces of the operating system (OS), allocates and looks down blocks of memory. The memory allocation subroutines then de-allocates the memory blocks based on whether or not the memory blocks fall within the pre-selected range of physical memory locations. The physical memory locations of the blocks locked down are discovered using the driver. The driver takes the virtual address of the specified memory locations and returns with a corresponding physical address. The memory allocation subroutines provide functions that allow the program developer to specify the number of physical pages to allocate and a range of physical addresses and comprises algorithm(s) that allocates the physical memory within the selected range.

Abstract: A method and system for allocating pre-selected physical memory locations to an application executing on a data processing system. A kernel mode driver and memory allocation subroutines are provided. The memory allocation subroutines, interacting with the programming interfaces of the OS allocates and locks down blocks of memory. The memory allocation subroutines then deallocates the memory blocks based on whether or not the memory blocks fall within the pre-selected range of physical memory locations. The physical memory locations of the blocks locked down are discovered using the driver. The driver takes the virtual address of the specified memory locations and returns with a corresponding physical address. This process involves the use of AWE APIs of the OS, which allows the physical memory to be locked down. The memory allocation subroutines provides functions that allow the program developer to specify the number of physical pages to allocate and a range of physical addresses.

Abstract: A method and system for maintaining a routing path between a selected workstation within a multisegment local area network and a mobile workstation wherein individual segments within the multisegment local area network are interconnected by a router device and wherein selected segments within the multisegment local area network include radio frequency transceivers adapted to provide a wireless communications link with mobile workstations. Each time communication is established between a mobile workstation and a selected workstation within the multisegment local area network via a radio frequency transceiver a routing table entry is established which identifies a segment location for the mobile workstation within a routing table associated with each router device within the multisegment local area network.

Abstract: A micro processor controlled user programmable communications multiplexer subsystem (herein referred to by the symbol PCS) capable of transmitting and receiving data on any one or more of 32 communications lines simultaneously. Each line may be dynamically assigned to a variety of communication characteristics, such as line speeds, character lengths, synchronous, or asynchronous operation, and code structures as well as protocol selections.The system of the invention provides the capability for the user to write his communications programs using novel operations commands that provide code structure and protocol independence as well as communication line independence. Various hardware features and queuing techniques are employed in order to maintain high transmission rates.Variable line scanning in the Teleprocessing Time Division Multiplexer of the PCS is programmably permissible; i.e.