Abstract: The present invention relates to a thermoplastic ABS composition reinforced with natural fibres, which comprises an ABS polymer, natural fibres, a compatibilizing polymer, and processing aids comprising a lubricant and titanium dioxide. It relates also to a moulded article prepared from the thermoplastic composition and to its use in extrusion, injection, compression moulding and 3D printing.

Abstract: The present invention relates to a thermoplastic ABS composition reinforced with natural fibres, which comprises an ABS polymer, natural fibres, a compatibilizing polymer, and processing aids comprising a lubricant and titanium dioxide. It relates also to a moulded article prepared from the thermoplastic composition and to its use in extrusion, injection, compression moulding and 3D printing.

Abstract: According to one embodiment of the present invention, a monitoring system for monitoring resource consumption of at least one monitored site is disclosed. The system comprises a plurality of sensors deployed at different locations of the at least one monitored site, the sensors being configured to provide measurement values over a data network; a data association facility connected to the data network, the data association facility being configured to associate each measurement value with a location information within the at least one monitored site based on a hierarchical model of the monitored site and type information associated with a corresponding sensor of the plurality of sensors; and a graphical interface facility connected to the data network, the graphical interface facility being configured to selectively display the plurality of measurement values based on the associated location information and type information.

Abstract: A system includes a sub-binary radix digital-to-analog converter (DAC) that converts a digital input signal to an analog output signal based on a sub-radix DAC code. A radix conversion module performs radix conversion on the digital input signal. To perform the radix conversion, the radix conversion module associates bit positions corresponding to the digital input signal with respective analog weights and converts the digital input signal to the sub-radix DAC code based on the respective analog weights.

Abstract: An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N>m, and N is the sum of NL and NS.

Abstract: A system includes an NL bit digital to analog converter (DAC) ladder module having NL ladder resistors connected in parallel, NL series resistors connected in series between the NL ladder resistors, and a plurality of switches. NL is an integer greater than one. Adjacent pairs of the plurality of switches are connected in series with respective ones of the ladder resistors. On resistances of each of the plurality of switches are approximately equal. A switch control module provides a plurality of switch control signals to respective ones of the plurality of switches.

Abstract: A driver circuit uses a feedback loop having a programmable timer and timer logic to adjust a slew rate delay period used to accommodate slewing current when charging or discharging a load capacitor, and to increase the current limit during the slew rate delay period by selecting a larger input current reference value. Increasing the current limit provides for a faster settling time. The value of each input current reference value can be programmed. The programmable timer and the timer logic can be configured to coordinate the slew rate delay period and the selected input current reference value. The slew rate delay period can be adjusted based on which input current reference value is applied.

Abstract: A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.

Abstract: A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.

Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.

Abstract: The present invention is directed to a method of identifying duplicate data elements in large data sets. This involves receiving the data sets. Dividing each data element in the data set into a series of data segments to define data keys. Generating an intermediate value for the each element in the data set using summed values for the data keys. Sorting the data entries using the intermediate values. Sorting the matched intermediate value entries using the data keys. Identifying the duplicate data elements in the data set.

Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.

Abstract: The present invention is directed to a method of identifying duplicate data elements in large data sets. This involves receiving the data sets. Dividing each data element in the data set into a series of data segments to define data keys. Generating an intermediate value for the each element in the data set using summed values for the data keys. Sorting the data entries using the intermediate values. Sorting the matched intermediate value entries using the data keys. Identifying the duplicate data elements in the data set.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. A reference voltage is coupled to each of a first and second comparator integrated on the chip. A supply voltage is compared to the reference voltage in a comparator to determine overvoltage or undervoltage conditions. The results of the comparison are stored and sizing and placing of at least one decoupling circuit in the circuit design is made based on the stored determinations.

Abstract: A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.

Abstract: Digital to analog converters having a hybrid two-stage structure. The first stage is a differential segmented current DAC controlled by the MSBs (most significant bits) of input data. The second stage is a resistor string DAC controlled by the LSBs (least significant bits) of the input data to interpolate between the differential outputs of the first stage. The resistor string is directly connected to the current DAC without the need of buffer amplifiers. Instead, a replica circuit is used to prevent the second-stage resistor string from loading the first stage current DAC. Compensation techniques are described.

Abstract: Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.

Abstract: Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.

Abstract: Asynchronous and synchronous deglitch controllers controlling switches of sample and hold circuits for deglitching digital to analog converters. Asynchronous and synchronous deglitch controllers detect transitions in the state of the digital input code to trigger or allow a one shot pulse to cause sample and hold circuits to go into hold mode for the period of the one shot pulse. Secondary glitch cancellation circuitry models the environment of the sample and hold circuit to emulate secondary glitch impulse generation. A differential amplifier substantially cancels secondary glitches related to the parasitic charges generated by the switching of the sample and hold circuit.