Abstract: Methods and systems are provided to facilitate network egress fairness between applications. At an egress port of a network, an arbitrator can provide fairness-based traffic shaping to data associated with applications. The desired fairness-based traffic shaping can be provided based on bandwidth, traffic classes, or other parameters. Consequently, the egress link's bandwidth can be allocated with fairness among the applications.

Abstract: A network interface controller (NIC) capable of efficient load balancing among the hardware engines is provided. The NIC can be equipped with a plurality of ordering control units (OCUs), a queue, a selection logic block, and an allocation logic block. The selection logic block can determine, from the plurality of OCUs, an OCU for a command from the queue, which can store one or more commands. The allocation logic block can then determine a selection setting for the OCU, select an egress queue for the command based on the selection setting, and send the command to the egress queue.

Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: The efficient storage of transformation information in a switch is provided. A respective port of the switch can include a memory device capable of storing transformation information. During operation, the switch can apply a selection mechanism to the transformation information learned at the switch for identifying a target port. The switch can then store the information in the memory device of the target port. Upon receiving a packet, the ingress port can apply the selection mechanism to the header information of the packet for determining a location of a first piece of transformation information associated with the packet. The ingress port can obtain the first piece of transformation information by looking up the header information in the location and storing it in a local memory device. The ingress port can then transform the packet based on the first piece of transformation information for determining an egress port for the packet.

Abstract: A method for conducting a network performance analysis, the method comprising measuring latencies of a plurality of packets communicated over a network includes determining latency representations for a plurality of levels of the network, for a plurality of communication routes, and/or for a plurality of communication types. The latency representations comprise the latency measurements, statistical representations of the latency measurements, and/or latency metrics derived from the latency measurements. The method includes comparing the determined latency representations to expected latency representations, the expected latency representations comprising expected latencies, expected statistical representation of latencies, and/or expected latency metrics.

Abstract: A network interface controller (NIC) capable of efficiently utilizing an output buffer is provided. The NIC can be equipped with an output buffer, a host interface, an injector logic block, and an allocation logic block. The output buffer can include a plurality of cells, each of which can be a unit of storage in the output buffer. If the host interface receives a command from a host device, the injector logic block can generate a packet based on the command. The allocation logic block can then determine whether the packet is a multi-cell packet. If the packet is a multi-cell packet, the allocation logic block can determine a virtual index for the packet. The allocation logic block can then store, in an entry in a data structure, the virtual index, and a set of physical indices of cells storing the packet.

Abstract: A method for conducting a network performance analysis, the method comprising measuring latencies of a plurality of packets communicated over a network includes determining latency representations for a plurality of levels of the network, for a plurality of communication routes, and/or for a plurality of communication types. The latency representations comprise the latency measurements, statistical representations of the latency measurements, and/or latency metrics derived from the latency measurements. The method includes comparing the determined latency representations to expected latency representations, the expected latency representations comprising expected latencies, expected statistical representation of latencies, and/or expected latency metrics.

Abstract: A network interface controller (NIC) capable of facilitating fine-grain flow control (FGFC) is provided. The NIC can be equipped with a network interface, an FGFC logic block, and a traffic management logic block. During operation, the network interface can determine that a control frame from a switch is associated with FGFC. The network interface can then identify a data flow indicated in the control frame for applying the FGFC. The FGFC logic block can insert information from the control frame into an entry of a data structure stored in the NIC. The traffic management logic block can identify the entry in the data structure based on one or more fields of a packet belonging to the flow. Subsequently, the traffic management logic block can determine whether the packet is allowed to be forwarded based on the information in the entry.

Abstract: A data-driven intelligent networking system that can facilitate global fairness is provided. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and enforce global fairness on a per-flow basis.

Abstract: A network interface controller (NIC) capable of efficiently utilizing an output buffer is provided. The NIC can be equipped with an output buffer, a host interface, an injector logic block, and an allocation logic block. The output buffer can include a plurality of cells, each of which can be a unit of storage in the output buffer. If the host interface receives a command from a host device, the injector logic block can generate a packet based on the command. The allocation logic block can then determine whether the packet is a multi-cell packet. If the packet is a multi-cell packet, the allocation logic block can determine a virtual index for the packet. The allocation logic block can then store, in an entry in a data structure, the virtual index, and a set of physical indices of cells storing the packet.

Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

Abstract: A network interface controller (NIC) capable of facilitating fine-grain flow control (FGFC) is provided. The NIC can be equipped with a network interface, an FGFC logic block, and a traffic management logic block. During operation, the network interface can determine that a control frame from a switch is associated with FGFC. The network interface can then identify a data flow indicated in the control frame for applying the FGFC. The FGFC logic block can insert information from the control frame into an entry of a data structure stored in the NIC. The traffic management logic block can identify the entry in the data structure based on one or more fields of a packet belonging to the flow. Subsequently, the traffic management logic block can determine whether the packet is allowed to be forwarded based on the information in the entry.

Abstract: Methods and systems are provided to facilitate network egress fairness between applications. At an egress port of a network, an arbitrator can provide fairness-based traffic shaping to data associated with applications. The desired fairness-based traffic shaping can be provided based on bandwidth, traffic classes, or other parameters. Consequently, the egress link’s bandwidth can be allocated with fairness among the applications.

Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

Abstract: A network interface controller (NIC) capable of efficient packet injection into an output buffer is provided. The NIC can be equipped with an output buffer, a plurality of injectors, a prioritization logic block, and a selection logic block. The plurality of injectors can share the output buffer. The prioritization logic block can determine a priority associated with a respective injector based on a high watermark and a low watermark associated with the injector. The selection logic block can then determine, from the plurality of injectors, a subset of injectors associated with a buffer class and determine whether the subset of injectors includes a high-priority injector. Upon identifying a high-priority injector in the subset of injectors, the selection logic block can select the high-priority injector for injecting a packet in the output buffer.

Abstract: Methods and systems are provided to facilitate network egress fairness between applications. At an egress port of a network, an arbitrator can provide fairness-based traffic shaping to data associated with applications. The desired fairness-based traffic shaping can be provided based on bandwidth, traffic classes, or other parameters. Consequently, the egress link's bandwidth can be allocated with fairness among the applications.

Abstract: Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic while applying injection limits to different traffic classes at an ingress edge port. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. Furthermore, an edge switch can dynamically allocate the ingress port bandwidth among the traffic classes that are active at a given moment.

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

Abstract: A network interface controller (NIC) capable of efficiently utilizing an output buffer is provided. The NIC can be equipped with an output buffer, a host interface, an injector logic block, and an allocation logic block. The output buffer can include a plurality of cells, each of which can be a unit of storage in the output buffer. If the host interface receives a command from a host device, the injector logic block can generate a packet based on the command. The allocation logic block can then determine whether the packet is a multi-cell packet. If the packet is a multi-cell packet, the allocation logic block can determine a virtual index for the packet. The allocation logic block can then store, in an entry in a data structure, the virtual index, and a set of physical indices of cells storing the packet.