Abstract: A structure including a first fin-type field effect transistor (finFET) in a first semiconductor fin. The first finFET includes a channel region between a first source/drain (S/D) region and a second S/D region; and a gate all around (GAA) structure. The GAA structure includes an outer gate region over the channel region and a buried gate region under of the channel region and extending between the first S/D region and the second S/D region. The outer gate region and the buried gate region each include a gate metal layer and a gate dielectric layer. The gate dielectric layer is thicker in the buried gate region than in the outer gate region.

Abstract: A structure and method include a transistor with semiconductor nanosheets, which extend between source/drain regions and which include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet. The transistor includes inner gate sections below the center portions of each semiconductor nanosheet and an outer gate section with a horizontal portion above the center portion of the uppermost semiconductor nanosheet and with vertical portions on opposing sides of the semiconductor nanosheets and inner gate sections. Inner spacers are below the end portions of each semiconductor nanosheet. Outer spacers are adjacent the sidewalls of the outer gate section (including above end portions of the uppermost semiconductor nanosheet), are wider than the inner spacers, and extend onto proximal portions of the source/drain regions. Additional outer spacers are adjacent to the outer spacers (e.g.

Abstract: Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.

Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

Abstract: Embodiments of the disclosure provide a gate structure over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A first gate structure extends over the first edge, and entirely covers the first edge and the first corner segment of the semiconductor region.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.