Patents by Inventor David Chartrand

David Chartrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7791252
    Abstract: An ultrasonic imaging system wherein an exemplary system includes an array of transducer elements arranged along a first plane for transmitting first signals and receiving reflected signals for image processing. Circuit structures each have a major surface positioned in a co-planar orientation with respect to a major surface of another of the circuit structures to provide a sequence of the structures in a stack-like formation. Electrical connections are formed between adjacent circuit structures in the sequence. A connector region on each circuit structure includes a distal portion extending away from the major surface-with distal portions of connector regions of adjacent structures spaced apart from one another. A first wiring pattern extends from the major surface to the distal portion of the connector region.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: September 7, 2010
    Assignee: General Electric Company
    Inventors: Charles Edward Baumgartner, Robert Stephen Lewandowski, Kevin Matthew Durocher, David Chartrand
  • Publication number: 20080178677
    Abstract: An ultrasonic imaging system (200). An exemplary system includes an array of transducer elements (50) arranged along a first plane (P1) for transmitting first signals and receiving reflected signals for image processing. Circuit structures (10, 20, 30, 40) each have a major surface (1a) positioned in a co-planar orientation with respect to a major surface of another of the circuit structures to provide a sequence of the structures (10, 20, 30, 40) in a stack-like formation. Electrical connections (34, 47) are formed between adjacent circuit structures in the sequence. A connector region (1b or 1b?) on each circuit structure includes a distal portion (1c or 1c?) extending away from the major surface (1a), with distal portions (1c, 1c?) of connector regions of adjacent structures spaced apart from one another. A first wiring pattern (41, 45, 46) extends from the major surface to the distal portion of the connector region.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventors: Charles Edward Baumgartner, Robert Stephen Lewandowski, Kevin Matthew Durocher, David Chartrand
  • Patent number: 6996883
    Abstract: A transducer is tuned to a desired impedance by building piezoelectric assemblies of multiple layers, each layer acting as a parallel capacitor. Piezoelectric layers are preferably constructed by plating or otherwise placing a conducting perimeter around a piezoelectric substrate. Gaps are suitably formed in the conducting layer by dicing or otherwise to form distinct electrical conducting regions on each layer. Piezoelectric layers are then suitably placed such that positive and negative conducting regions on each layer contact positive and negative regions on other layers. Layers are suitably joined by epoxy or by any other joining technique.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: February 14, 2006
    Assignee: General Electric Company
    Inventors: Sanjay Chandran, David Chartrand
  • Publication number: 20030127947
    Abstract: A transducer is tuned to a desired impedance by building piezoelectric assemblies of multiple layers, each layer acting as a parallel capacitor. Piezoelectric layers are preferably constructed by plating or otherwise placing a conducting perimeter around a piezoelectric substrate. Gaps are suitably formed in the conducting layer by dicing or otherwise to form distinct electrical conducting regions on each layer. Piezoelectric layers are then suitably placed such that positive and negative conducting regions on each layer contact positive and negative regions on other layers. Layers are suitably joined by epoxy or by any other joining technique.
    Type: Application
    Filed: January 24, 2003
    Publication date: July 10, 2003
    Applicant: Parallel Design, Inc.
    Inventors: Sanjay Chandran, David Chartrand
  • Patent number: 6552471
    Abstract: A transducer is tuned to a desired impedance by building piezoelectric assemblies of multiple layers, each layer acting as a parallel capacitor. Piezoelectric layers are preferably constructed by plating or otherwise placing a conducting perimeter around a piezoelectric substrate. Gaps are suitably formed in the conducting layer by dicing or otherwise to form distinct electrical conducting regions on each layer. Piezoelectric layers are then suitably placed such that positive and negative conducting regions on each layer contact positive and negative regions on other layers. Layers are suitably joined by epoxy or by any other joining technique.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 22, 2003
    Assignee: Parallel Design, Inc.
    Inventors: Sanjay Chandran, David Chartrand