Patents by Inventor David Chevrie

David Chevrie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated package
    Patent number: 8237256
    Abstract: A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: August 7, 2012
    Assignee: Ipdia
    Inventors: Fabrice Verjus, Jean-Marc Yan-Nou, David Chevrie, Francois LeCornec, Nicolaas J. A. Van Veen
  • INTEGRATED PACKAGE
    Publication number: 20100308450
    Abstract: A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.
    Type: Application
    Filed: February 8, 2010
    Publication date: December 9, 2010
    Inventors: Fabrice Verjus, Jean-Marc Yan-Nou, David Chevrie, Francois LeCornec, Nicolaas J.A. Van Veen