Patents by Inventor David Chiong

David Chiong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER EFFICIENT PREDRIVER WITH NMOS MULTIPLEXER
    Publication number: 20250247094
    Abstract: A predriver circuit includes a voltage reference node, and a set of branches coupled to the voltage reference node. Each branch comprises a set of n-type metal-oxide semiconductor (NMOS) transistors. The predriver circuit further includes an active inductor coupled to the voltage reference node, and an amplifier. The input of the amplifier is coupled to the voltage reference node, and an output of the amplifier is coupled to a predriver output.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Inventors: Steve Fang, David Chiong, Raj Anantha Rao
  • Multi-GHZ fully synthesizable CMOS fractional divider
    Patent number: 10469088
    Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 5, 2019
    Assignee: Ambarella, Inc.
    Inventors: Tu-I Tsai, David Chiong, Dennis He, Chien-Tang Hu
  • Multi-GHz fully synthesizable CMOS fractional divider
    Patent number: 10236889
    Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: March 19, 2019
    Assignee: Ambarella, Inc.
    Inventors: Tu-I Tsai, David Chiong, Dennis He, Chien-Tang Hu