Patents by Inventor David Chong

David Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250000025
    Abstract: A system for a work vehicle includes an arm and an actuator system. The actuator system includes a drive component and a linkage assembly. The linkage assembly is coupled to the arm and the drive component. The drive component is configured to drive the linkage assembly to rotate the arm from a first position in which the arm extends forward of a working component of the work vehicle to a second position in which the arm is positioned rearward of the working component of the work vehicle.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Cory Douglas Hunt, Jeremy Kuelker, Stephen Todderud, David Chong, Luis Lara, Shane Fanning, Joseph Russell Woelfling
  • Patent number: 10916683
    Abstract: A light emitting device includes a vertical via through the P-type semiconductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 9, 2021
    Assignee: Lumileds LLC
    Inventors: David Chong, Yeow-Meng Teo
  • Publication number: 20200144454
    Abstract: A light emitting device includes a vertical via through the P-type semiconductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.
    Type: Application
    Filed: January 7, 2020
    Publication date: May 7, 2020
    Applicant: Lumileds Holding B.V.
    Inventors: David CHONG, Yeow-Meng TEO
  • Patent number: 10529894
    Abstract: A light emitting device includes a vertical via through the P-type semiconductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: January 7, 2020
    Assignee: Lumileds Holding B.V.
    Inventors: David Chong, Yeow-Meng Teo
  • Publication number: 20180337308
    Abstract: A light emitting device includes a vertical via through the P-type semi-conductor layer and the active layer. Using a vertical via reduces quantum well damage, allows shortening of P-N spacing, and allows increased reflective area. A dielectric structure is formed in the via to provide a sloped wall that extends to an upper surface of the device. Another dielectric layer covers the upper surface and the sloped wall, and provides select contacts to the semiconductor layers. A metal layer is subsequently applied. Because the dielectric layers provide a continuous slope from the surface of the device, the metal layer does not include a vertical drop. Because the active layer does not extend into the via, the contact to the N-type semiconductor layer may be situated closer to the wall of the via, increasing the area available for a reflective layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: November 22, 2018
    Applicant: Lumileds Holding B.V.
    Inventors: David CHONG, Yeow-Meng TEO
  • Patent number: 9159656
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 13, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Publication number: 20140167238
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Application
    Filed: September 5, 2013
    Publication date: June 19, 2014
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Patent number: 8664752
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Publication number: 20130307134
    Abstract: In one implementation, a method of forming a conductive device can include depositing a non-conductive epoxy on a first portion of a lower surface of a semiconductor die, and can include depositing a conductive epoxy on a second portion of the lower surface of the semiconductor die.
    Type: Application
    Filed: July 22, 2013
    Publication date: November 21, 2013
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Jatinder KUMAR, David CHONG
  • Patent number: 8525321
    Abstract: In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 3, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jatinder Kumar, David Chong
  • Publication number: 20130009309
    Abstract: In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Inventors: Jatinder Kumar, David Chong
  • Publication number: 20120181675
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Patent number: 8110447
    Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: February 7, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Lay Yeap Lim, David Chong
  • Publication number: 20110159864
    Abstract: The present invention relates to an electronic equipment mode switching apparatus and method based on a skin contact made by a user using the electronic equipment, thereby being capable of minimizing the power consumption of electronic equipment and also of instantly operating electronic equipment as soon as skin contact is made. The electronic equipment mode switching apparatus includes skin contact detection means for detecting electricity generated when a user's skin is touched, logic circuit means for generating a mode switching signal to switch a power supply mode of an electronic device when skin contact is detected by the skin contact detection means, and mode switching means for switching the power supply mode of the electronic device in response to the mode switching signal generated by the logic circuit means.
    Type: Application
    Filed: October 5, 2010
    Publication date: June 30, 2011
    Inventors: June Min Park, David Chong
  • Publication number: 20100258925
    Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
  • Publication number: 20090236711
    Abstract: A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 24, 2009
    Inventors: Lay Yeap Lim, David Chong
  • Patent number: 7579680
    Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 25, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: David Chong, Hun Kwang Lee
  • Publication number: 20090189261
    Abstract: Semiconductor packages with a reduced-height die pad and associated methods for making and using these semiconductor packages are described. The semiconductor packages include a lead frame with die pad of reduced height so the die pad has a height that is less than that of the lead frame. The semiconductor packages may comprise an isolated and/or a fused lead finger with a portion of an upper surface of the isolated lead finger that is removed to form a concavity to which one or more bond wires may be bonded. The upper surface of the isolated lead finger may be removed so the isolated lead finger has a height that is less than the height of the lead frame. And a perimeter of a bottom surface of the fused lead finger may be removed. Other embodiments are described.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Inventors: Lay Yeap Lim, David Chong
  • Publication number: 20080036054
    Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.
    Type: Application
    Filed: August 24, 2007
    Publication date: February 14, 2008
    Inventors: David Chong, Hun Lee
  • Patent number: 7323361
    Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: January 29, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: David Chong, Hun Kwang Lee