Patents by Inventor David Chong Sook Lim

David Chong Sook Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8003447
    Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: August 23, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Edwin Man Fai Lee, David Chong Sook Lim, Adriano M. Vilas-Boas
  • Publication number: 20110078899
    Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 7, 2011
    Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Lee Man Fai Edwin, David Chong Sook Lim, Adriano M. Vilas-Boas
  • Patent number: 7868432
    Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: January 11, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Lee Man Fai Edwin, David Chong Sook Lim, Adriano M. Vilas-Boas
  • Publication number: 20070187807
    Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.
    Type: Application
    Filed: February 8, 2007
    Publication date: August 16, 2007
    Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Lee Man Fai Edwin, David Chong Sook Lim, Adriano M. Vilas-Boas
  • Publication number: 20040080056
    Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. A flattened ball is attached to die contacts and a gold wire runs parallel to the die and then to a via on the substrate. The wire may be attached to the flattened ball by a wedge technique or other such known techniques. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.
    Type: Application
    Filed: September 17, 2003
    Publication date: April 29, 2004
    Inventors: David Chong Sook Lim, Hun Kwang Lee, Howard Allen, Stephen Martin
  • Publication number: 20020140070
    Abstract: A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the appropriate mount locations of the printed circuit board. The die is attached to the substrate using a non-electrically-conductive material. This packaging enables a fabricator to make die of one orientation type, die down, and use that die in a die-up package, thereby saving on fabrication costs.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Applicant: Fairchild Semiconductor Corp.
    Inventors: David Chong Sook Lim, Hun Kwang Lee, Howard Allen, Stephen Martin