Patents by Inventor David Church

David Church has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ENHANCED EPROM STRUCTURES WITH ACCENTUATED HOT ELECTRON GENERATION REGIONS
    Publication number: 20030122177
    Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
    Type: Application
    Filed: December 20, 2001
    Publication date: July 3, 2003
    Inventor: Michael David Church
  • Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions
    Publication number: 20030119236
    Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Inventor: Michael David Church
  • Enhanced EPROM structures with accentuated hot electron generation regions
    Patent number: 6566705
    Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: May 20, 2003
    Assignee: Intersil Americas, Inc.
    Inventor: Michael David Church
  • Method of fabricating enhanced EPROM structures with accentuated hot electron generation regions
    Patent number: 6492225
    Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: December 10, 2002
    Assignee: Intersil Americas Inc.
    Inventor: Michael David Church
  • BiCMOS devices
    Patent number: 5856695
    Abstract: A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: January 5, 1999
    Assignee: Harris Corporation
    Inventors: Akira Ito, Michael David Church
  • Method of fabricating BiCMOS devices
    Patent number: 5851864
    Abstract: A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: December 22, 1998
    Assignee: Harris Corporation
    Inventors: Akira Ito, Michael David Church