Patents by Inventor David Colavito

David Colavito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6525340
    Abstract: A field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the FET includes an active semiconductor region defined upon a substrate, the active semiconductor region further having a mesa region formed therein. The FET also includes a gate formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. The FET further includes a source region defined within a first area of the semiconductor region, the first region being located over an insulating layer, and a drain region defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate. In another exemplary embodiment, one of the source region or drain region is defined within a top surface of the mesa region.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: February 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: David Colavito, Nivo Rovedo
  • Publication number: 20020179905
    Abstract: A method for forming a field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further having a mesa region formed therein. A gate is formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. Then, a source region is defined within a first area of the semiconductor region, the first region being located over an insulating layer. A drain region is defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 5, 2002
    Inventors: David Colavito, Nivo Rovedo