Patents by Inventor David Conklin

David Conklin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12381118
    Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: August 5, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Andrew Weloth, Daniel Fulford, Anthony Schepis, Mark I. Gardner, H. Jim Fulford, Anton Devilliers, David Conklin
  • Publication number: 20250226265
    Abstract: Aspects of the present disclosure provide a method for correcting an overlay error by shifting lithographic patterns to be formed on a wafer according to a bow measurement of the wafer. For example, the method can include receiving a first location at which one or more first semiconductor elements are to be formed on a first wafer, measuring the first wafer to identify a first bow measurement of the first wafer, calculating a second location that is shifted from the first location based on the first bow measurement, and forming the first semiconductor elements on the first wafer at the second location.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 10, 2025
    Applicant: Tokyo Electron Limited
    Inventors: Dave POWER, David CONKLIN, Anthony SCHEPIS
  • Publication number: 20250191970
    Abstract: A method of patterning a substrate includes forming a hardmask over an underlying layer supported by a substrate, forming antispacer trenches over the hardmask, and forming fully self-aligned vias (FSAVs) extending from the hardmask into the underlying layer. The hardmask includes hardmask line features defining hardmask trenches extending in a first direction. The antispacer trenches extend in a second direction nonparallel to the first direction. The FSAVs extend into the underlying layer at intersections of the hardmask trenches and the antispacer trenches. The FSAVs are self-aligned on two sides by sidewalls of the hardmask trenches and self-aligned on the remaining sides by sidewalls of the antispacer trenches.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Inventors: David Power, David Conklin
  • Publication number: 20250189901
    Abstract: A method of processing a substrate, including generating a mask density map based on a photomask, the mask density map spatially mapping transparent regions of the photomask and blocking regions of the photomask that block radiation at a predetermined wavelength; generating a flare map based on the mask density map, the flare map spatially indicating a projected amount of received radiation in excess of a desired amount of radiation at each coordinate location on the photomask; and generating a critical dimension modification map based on the flare map, the critical dimension modification map including a modification energy dosage for each coordinate location on the photomask.
    Type: Application
    Filed: March 27, 2024
    Publication date: June 12, 2025
    Applicant: Tokyo Electron Limited
    Inventors: Daniel FULFORD, David POWER, David CONKLIN
  • Publication number: 20250172877
    Abstract: Reversible overcoat compositions for overcoating structures during semiconductor microfabrication are described. An example composition includes a first solute with an organic hydroxy functional group, a second solute with an enol ether functional group, and an organic solvent system, with a mole ratio between all of the organic hydroxy functional groups of the first solute and all of the enol ether functional groups of the second solute being between 2.0 and 4.0.
    Type: Application
    Filed: March 27, 2024
    Publication date: May 29, 2025
    Inventors: Charlotte Cutler, Michael Murphy, David Conklin
  • Publication number: 20250029837
    Abstract: A method for forming a semiconductor device can include coating a reversible overcoat layer over first mandrels on a substrate, inducing a crosslinking reaction within the reversible overcoat layer that renders the reversible overcoat layer insoluble to a developer and forms a crosslinked overcoat layer, diffusing acid particles from the first mandrels into first portions of the crosslinked overcoat layer, inducing a de-crosslinking reaction within the first portions of the crosslinked overcoat layer to form de-crosslinked regions, where unmodified regions of the crosslinked overcoat layer form second mandrels, and selectively removing the de-crosslinked regions with the developer such that the first mandrels and the second mandrels form a mandrel pattern over the substrate, where the developer has a solubility distance in a range of zero to seven in a Hansen Solubility Parameter space relative to methyl isobutyl carbinol.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 23, 2025
    Inventors: David Conklin, Charlotte Cutler, Michael Murphy, Jodi Grzeskowiak
  • Publication number: 20240419074
    Abstract: A method includes forming a plurality of first mandrels over a substrate, forming an overcoat layer over the plurality of first mandrels, and inducing a crosslinking reaction within the overcoat layer and form a crosslinked overcoat layer. The method further includes exposing the substrate to a radiation to generate a plurality of acid molecules within the plurality of first mandrels, diffusing a portion of the plurality of acid molecules from the plurality of first mandrels into portions of the crosslinked overcoat layer, and inducing a decrosslinking reaction within the portions of the crosslinked overcoat layer and form de-crosslinked regions. Unmodified regions of the crosslinked overcoat layer form a plurality of second mandrels. The method further includes selectively removing the de-crosslinked regions. The plurality of first mandrels and the plurality of second mandrels form a mandrel pattern over the substrate.
    Type: Application
    Filed: March 25, 2024
    Publication date: December 19, 2024
    Inventors: Michael Murphy, Jacob Dobson, Jodi Grzeskowiak, David Conklin
  • Publication number: 20240363340
    Abstract: A method of processing a substrate that includes: loading a substrate into a deposition tool, the substrate including a major working surface and a backside surface opposite the major working surface, the major working surface including a semiconductor device structure; in the deposition tool, performing a solution-based process to form a film on the backside surface, the film being an inorganic-based film or an organic-inorganic hybrid film.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 31, 2024
    Inventors: Charlotte Cutler, Michael Murphy, David Conklin
  • Publication number: 20240203797
    Abstract: Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Andrew WELOTH, Daniel FULFORD, Anthony SCHEPIS, Mark I. GARDNER, H. Jim FULFORD, Anton DEVILLIERS, David CONKLIN
  • Publication number: 20240203778
    Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Applicant: Tokyo Electron Limited
    Inventors: David POWER, David CONKLIN, Anthony SCHEPIS, Andrew WELOTH, Anton DEVILLIERS
  • Publication number: 20240168384
    Abstract: In certain embodiments, a method includes forming, by photolithography on a semiconductor wafer, first patterned features (PFs) including first photoresist structures (PRSs) having a first width and first recesses having a second width less than the first width and greater than a target width; forming, via anti-spacer patterning processing, second PFs including second PRSs having a third width less than the first width, first overcoat structures (OCSs) of the second width interspersed between second PRSs, and second recesses having a fourth width less than the target width; and forming, via acid diffusion processing, third PFs including third PRSs having a fifth width, second OCSs of the target width interspersed between third PRSs, and third recesses defined by third PRSs and second OCSs and having a sixth width greater than the fourth width, portions of first OCSs having been selectively removed using the acid diffusion processing to form second OCSs.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 23, 2024
    Inventors: Michael Murphy, Charlotte Cutler, David Conklin
  • Publication number: 20240030029
    Abstract: A method of patterning a substrate includes exposing a photoresist layer on the substrate with a pattern of actinic radiation to form a chemically reactive surface pattern, and coating, at the track system, a spin-on-material to convert the chemically reactive surface pattern to a photoresist surface mask pattern. The method further includes etching the photoresist layer using the photoresist surface mask pattern as a first etch mask to form a photoresist mask pattern, and etching a layer to be etched with the photoresist mask pattern as a second etch mask.
    Type: Application
    Filed: January 4, 2023
    Publication date: January 25, 2024
    Inventors: Charlotte Cutler, David Conklin
  • Publication number: 20230350303
    Abstract: A method of patterning an underlying layer that includes: depositing a metal-free polymer film over the underlying layer, exposing the film to an EUV to form an exposed region and a masked region of the film, the exposed region photoreacting to the EUV; selectively dry etching first portions of the film to form features including the remaining second portions of the film, an etch rate of the first portions being greater than that of the second portions of the film, the first portions being one of the exposed region and the masked region, the second portions being another of the exposed region and the masked region that is not the first portion, where a pitch of the features is below the feature size achievable with a 193 nm immersion lithography tool in a single patterning process; and patterning the underlying layer using the second portion as an etch mask.
    Type: Application
    Filed: March 30, 2023
    Publication date: November 2, 2023
    Inventors: Charlotte Cutler, David Conklin
  • Publication number: 20230352343
    Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 2, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey SMITH, David POWER, Eric Chih-Fang LIU, Anton J. DEVILLIERS, Kandabara TAPILY, Jodi GRZESKOWIAK, David CONKLIN, Michael MURPHY
  • Publication number: 20230290676
    Abstract: A method of patterning a substrate, where the method includes: forming first structures over a memorization layer, the first structures including a first row of lines that are parallel with each other and spaced apart from each other; executing a first anti-spacer formation process to form first trenches along sidewalls of the first structures and sidewalls of a first fill material, the first trenches defining a first etch pattern; transferring the first etch pattern into the memorization layer and removing materials above the memorization layer; forming second structures over the memorization layer, the second structures including a second row of lines that are parallel with each other and spaced apart, placement of the second row of lines being shifted relative to the first row of lines; executing a second anti-spacer formation process to form second trenches formed along sidewalls of the second structures and sidewalls of a second fill material, the second trenches defining a second etch pattern; and trans
    Type: Application
    Filed: November 17, 2022
    Publication date: September 14, 2023
    Inventors: David Power, David Conklin, Jodi Grzeskowiak, Michael Murphy
  • Publication number: 20230251570
    Abstract: A method of patterning a substrate by selective deprotection via dye diffusion. The method includes forming a photoresist pattern on the substrate from a layer of photoresist deposited on the substrate, depositing a first overcoat on the photoresist pattern, the first overcoat filling openings defined by the photoresist pattern and covering the photoresist pattern, the first overcoat including an organic film containing a dye. The method further includes diffusing the dye from the first overcoat a predetermined diffusion length into the photoresist pattern, resulting in diffusion regions in the photoresist pattern, and removing the first overcoat from the substrate. The method further includes activating the solubility-shifting agent in the diffusion regions of the photoresist pattern using a second actinic radiation, depositing a second overcoat on the substrate, and developing the substrate with a second developer resulting in removal of soluble portions of the diffusion regions of the photoresist pattern.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 10, 2023
    Inventors: Michael Murphy, Charlotte Cutler, David Conklin
  • Patent number: 11526088
    Abstract: Aspects of the present disclosure provide an imaging system. For example, in the imaging system a first light source can generate a first light beam of a first wavelength, a second light source can generate a second light beam of a second wavelength, the second light beam having power sufficient to pass through at least a portion of a thickness of a wafer, an alignment module can coaxially align the second light beam with the first light beam, a coaxial module can focus the coaxially aligned first and second light beams onto a first pattern located on a front side of the wafer and a second pattern located below the first pattern, respectively, and an image capturing module can capture a first image of the first pattern and a second image of the second pattern. The second image can be captured via quantum tunneling imaging or infrared (IR) transmission imaging.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: December 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. Devilliers, Anthony R. Schepis, David Conklin
  • Publication number: 20220336226
    Abstract: Techniques herein include methods for forming a direct write, tunable stress film and methods for correcting wafer bow using said stress film. The method can be executed on a coater-developer tool or track-based tool. The stress film can be based on a film that undergoes crosslinking/decrosslinking under external stimulus where direct write is achieved by, but is not limited to, 365 nm exposure and subsequent cure is used to “pattern-in” stress. No develop step may be required, which provides additional significant benefit in conserving film planarity. An amount of bow (or internal stress to create or affect a bow signature) can be tuned with exposure dose, bake temperature, bake time and number of bakes.
    Type: Application
    Filed: March 24, 2022
    Publication date: October 20, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Charlotte CUTLER, Michael MURPHY, David CONKLIN
  • Publication number: 20220050388
    Abstract: Aspects of the present disclosure provide an imaging system. For example, in the imaging system a first light source can generate a first light beam of a first wavelength, a second light source can generate a second light beam of a second wavelength, the second light beam having power sufficient to pass through at least a portion of a thickness of a wafer, an alignment module can coaxially align the second light beam with the first light beam, a coaxial module can focus the coaxially aligned first and second light beams onto a first pattern located on a front side of the wafer and a second pattern located below the first pattern, respectively, and an image capturing module can capture a first image of the first pattern and a second image of the second pattern. The second image can be captured via quantum tunneling imaging or infrared (IR) transmission imaging.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 17, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Anton J. DEVILLIERS, Anthony R. SCHEPIS, David CONKLIN
  • Publication number: 20220050386
    Abstract: Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 17, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Anton J. DEVILLIERS, Anthony R. SCHEPIS, David CONKLIN