Abstract: A method for manufacturing semiconductor devices can include forming an anti-spacer pattern including anti-spacer trenches, formed between a first patterned photoresist layer and a patterned overcoat layer, and extending along a first direction, forming a first patterned hard mask layer having first contact trenches extending along the first direction using the anti-spacer pattern, where the first patterned hard mask layer is formed from a first hard mask layer of underlying layers, forming a second patterned photoresist layer, where the second patterned photoresist layer includes contact-edge features and second contact trenches overlapping with the first contact trenches of the first patterned hard mask layer, where the contact-edge features and the second contact trenches extend in a second direction that is non-parallel with the first direction; and self-aligned etching using the second patterned photoresist layer and the first patterned hard mask layer to form third contact trenches.

Abstract: This disclosure provides methods and systems of processing a semiconductor wafer. One method includes obtaining wafer characterization metrology information of a wafer, the wafer including a plurality of dies, and generating a plurality of predicted die shapes based on the wafer characterization metrology information being input into a computing model. Each of the plurality of predicated die shapes corresponds to one of the plurality of dies of the wafer. The method further includes processing the wafer to obtain the plurality of dies and processing the plurality of dies based on the plurality of predicated die shapes.

Abstract: A composition for patterning substrates includes a monomer. The monomer includes a polymerizable unit, a thermally or photochemically activatable crosslinking structure, and an acid-cleavable de-crosslinking structure. The polymerizable unit includes an olefin.

Abstract: A method of forming a patterned metal layer on a substrate includes identifying at least one distortion zone in a design pattern of metal structures causing a Z-direction displacement of the substrate, inserting metal fill shapes as a fill pattern into the design pattern to reduce the Z-direction displacement in the at least one distortion zone, and forming the metal structures and the metal fill shapes on the substrate as the patterned metal layer. The method may further include calculating bond strength of the substrate based on the design pattern and the fill pattern and adjusting surface area of the metal fill shapes to increase the bond strength. A bonded substrate structure may then be formed by directly bonding a dielectric material of the patterned metal layer of the substrate to an additional substrate.

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

Abstract: Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.

Abstract: A method of patterning a substrate includes exposing a photoresist layer on the substrate with a pattern of actinic radiation to form a chemically reactive surface pattern, and coating, at the track system, a spin-on-material to convert the chemically reactive surface pattern to a photoresist surface mask pattern. The method further includes etching the photoresist layer using the photoresist surface mask pattern as a first etch mask to form a photoresist mask pattern, and etching a layer to be etched with the photoresist mask pattern as a second etch mask.

Abstract: A method of patterning a substrate includes forming a mandrel over the substrate, the mandrel including an extreme ultraviolet (EUV) resist, and depositing a first overcoat layer over the mandrel from a first solution, the first solution including a first solvent, a first polymer, and an agent generator or an acid. The method further includes selectively removing the first overcoat layer leaving a first mandrel portion surrounded by a second mandrel portion, the second mandrel portion being formed by modifying an outer portion of the mandrel by the first overcoat layer. The method further includes depositing a second overcoat layer over the second mandrel portion from a second solution, the second overcoat layer being separated from the first mandrel portion by the second mandrel portion, the second solution including a second solvent, and a second polymer.

Abstract: A method includes providing a carrier substrate having a die bonded thereto, where the die includes a first alignment mark on a first surface. The method includes positioning a target substrate with a second surface on a substrate stage, where the target substrate includes a second alignment mark on the second surface. The method includes positioning the carrier substrate with respect to a die handler, where the die handler includes a third alignment mark. The method includes coupling the die to the die handler, where the step of coupling includes aligning the first alignment mark with the third alignment mark. The method includes positioning the coupled die and the die handler over the target substrate, where the step of positioning includes aligning the second alignment mark with at least one of the first alignment mark and the third alignment mark. The method includes bonding the first surface with the second surface.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a heating device that is configured to generate a certain pattern of heat. The heating device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of heat generated by the heating device can be applied to the semiconductor structure.

Abstract: A method for patterning a substrate, the method includes forming a first mask over the substrate, the first mask including first features and first spaces and exposing the substrate at a bottom of each first space; forming a second mask while retaining the first features, the second mask including second features and second spaces, the second features covering a portion of the substrate exposed by the first spaces; and either selectively depositing on or selectively removing material from the second features relative to the first features to change a width of each of the second features.

Abstract: Aspects of the present disclosure provide a method for correcting distortion of a semiconductor substrate. For example, the method can include receiving a semiconductor substrate with distortion, measuring the semiconductor substrate to identify the distortion in a plurality of positions on the semiconductor substrate, and implanting into the semiconductor substrate a lattice configuration signature according to the identified distortion in the positions such that the identified distortion of the semiconductor substrate is corrected.

Abstract: Aspects of the present disclosure provide an apparatus that heats a semiconductor structure while holding the semiconductor structure. For example, the apparatus can include a semiconductor structure holding device that is configured to hold the semiconductor structure. The apparatus can also include a light projection device that is configured to generate a certain pattern of light. The light projection device can be integrated with the semiconductor structure holding device such that when the semiconductor structure holding device is holding the semiconductor structure, the certain pattern of light generated by the light projection device is projected onto the semiconductor structure holding device and a corresponding certain pattern of heat is generated and transferred through the semiconductor structure holding device and applied to the semiconductor structure, in order to correct the shape and size of the semiconductor structure.

Abstract: An example method of processing a substrate includes patterning a photoresist deposited over the substrate to form a plurality of mandrels, and spin coating an overcoat material over the plurality of mandrels. The method includes exposing the substrate to an ultraviolet (UV) irradiation to generate acid in the plurality of mandrels; diffusing the acid into a portion of the overcoat material. The diffused acid induces a crosslinking reaction in the portion to form a crosslinked portion of the overcoat material. The method includes performing a developing process using a developing solution to remove the plurality of mandrels and the overcoat material except the crosslinked portion of the overcoat material.

Abstract: A method includes forming a photoresist layer over a substrate. The method further includes exposing the photoresist layer to a radiation to generate a first acid in exposed regions of the photoresist layer. The method further includes forming a trim layer over the photoresist layer. The trim layer includes a second acid. The method further includes performing a bake process on the substrate having the photoresist layer and the trim layer disposed thereon. Performing the bake process includes reacting the first acid with a material of the exposed regions to form first modified regions, diffusing the second acid from the trim layer into unmodified regions of the photoresist layer, and reacting the second acid with a material of the unmodified regions to form second modified regions. The method further includes and removing the trim layer, the first modified regions, and the second modified regions.

Abstract: Aspects of the present disclosure provide a method for chemical mechanical polishing (CMP) iso-dense bias compensation using z-height. For example, the method can include forming a dielectric material on a substrate within a first region to form one or more first dielectric layers that are spaced from one another, and forming on a first one of the first dielectric layers a first height correction layer that has a first height that is determined based on a first pattern density of the first region. The method can also include depositing a conductive material on the substrate to fill one or more first trenches surrounded by the first dielectric layers and the first height correction layer and cover the first dielectric layers and the first height correction layer, and performing a planarization process to planarize the conductive material and the first height correction layer until uncovering the first dielectric layers.

Abstract: An embodiment method of processing a substrate includes the patterning a photoresist layer formed over the substrate using a photolithographic technique, and spin coating a first overcoat material over the patterned photoresist layer, where the first overcoat material includes a photo-acid generator (PAG) and an acid amplifier (AA). The method includes exposing the first overcoat material to an ultraviolet (UV) irradiation to generate first acid from the PAG, where the first acid decomposes the AA to generate second acid, and a total amount of the second acid generated from the decomposition of the AA being greater than a total amount of first acid generated from the PAG. The method includes diffusing the second acid into a portion of the patterned photoresist layer, where the diffused second acid changes a solubility of the portion such that the portion becomes soluble in a developing solution.

Abstract: In certain embodiments, a method includes forming, by photolithography on a semiconductor wafer, first patterned features (PFs) including first photoresist structures (PRSs) having a first width and first recesses having a second width less than the first width and greater than a target width; forming, via anti-spacer patterning processing, second PFs including second PRSs having a third width less than the first width, first overcoat structures (OCSs) of the second width interspersed between second PRSs, and second recesses having a fourth width less than the target width; and forming, via acid diffusion processing, third PFs including third PRSs having a fifth width, second OCSs of the target width interspersed between third PRSs, and third recesses defined by third PRSs and second OCSs and having a sixth width greater than the fourth width, portions of first OCSs having been selectively removed using the acid diffusion processing to form second OCSs.

Abstract: Aspects of the present disclosure provide an inspection system, which can include an image module and processing circuitry. The imaging module can image a wafer with a first light beam and a second light beam. The first light beam can be coaxially aligned with the second light beam, and image a first pattern located on a front side of a wafer to form a first image. The second light beam can image a second pattern located below the first pattern to form a second image via quantum tunneling imaging or infrared transmission imaging. The second light beam can have power sufficient to pass through at least a portion of a thickness of the wafer and reach the second pattern. The processing circuitry can perform image analysis on the first image and the second image to calculate an overlay value of the first and second patterns and/or defects of the wafer.

Abstract: Aspects of the present disclosure provide a die-to-wafer (D2W) shape correction and bonding method. For example, the method can include providing a wafer and a chiplet, forming a shape control layer on at least one of the wafer and the chiplet, activating the shape control layer according to a bow measurement of the at least one of the wafer and the chiplet to modify an internal stress of the shape control layer, and bonding the wafer and the chiplet, at least one of which has the shape control layer formed thereon that is activated according to the bow measurement of the at least one of the wafer and the chiplet.