Abstract: The invention relates to novel compounds of formula (1), or pharmaceutically acceptable salts thereof, for use in treatment of viral infection. The invention further relates to methods of treating viral infection by administering a therapeutically effective amount of the compound of formula (1).

Abstract: An embodiment includes a method of software utilization evaluation in a managed network. The method includes receiving a software parameter for a software implemented by a managed device in a managed network. The method includes obtaining status data of the software on the device. The status data indicating whether the software is in use at the device at a time. The method includes aggregating the status data to determine a software usage of the software at the device. Responsive to the software usage being below a usage threshold, the method includes generating software management action. The usage threshold being based on the software parameter. Responsive to a state at a management device, the method includes implementing the software management action to remotely modify at least one aspect of the managed device.

Abstract: The present disclosure relates to single guide RNA (sgRNA), Clustered Regularly Interspaced Short Palindromic Repeats (CRISPR)/CRISPR associate protein 9 (Cas9) system, and methods of use thereof for preventing, ameliorating or treating corneal dystrophies.

Abstract: The invention generally relates to compositions (including polynucleotides, constructs, fusion proteins, vectors, and cells) and methods of using such compositions for enhancing gene expression, protein production and viral replication. More specifically, the invention relates to use of m6A sequences and/or YTHDF polypeptides to enhance gene expression or viral replication.

Abstract: While 3D visualization is common within numerous other environments (like Movies, Gaming, Traffic reports, Weather reports, etc . . . ) it has only been utilized in the Information Technology (IT) space in so far as displaying virtual rooms or virtual physical environments (i.e. datacenter) and the IT equipment contained in that room. This focus of display may be valuable in some respects; however it is completely different from the concept proposed in this patent. This patent application focuses on a display of the application/service topology in a spatial environment much like a satellite floating in space. The topology is rendered as a collection of configuration items that form a holistic object—regardless of physical location or other physical attributes.

Abstract: A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.

Abstract: A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells.

Abstract: A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.

Abstract: A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.

Abstract: A water saving toilet flush system to selectively practice a partial or a full flush at the selection of the user is disclosed. A partial flush operation is initiated by depressing the control handle to commence the flush to connect a magnet assembly and to simultaneously unseat an associated flapper valve. Then the control lever is lifted to uncouple the magnet assembly and allow a float assembly to control seating of the flapper valve. A full flush operation is initiated in the same manner the partial flush operation is initiated. However, the control lever is allowed to remain depressed, causing the magnet assembly to remain coupled until a water level is low enough to cause the flapper valve to uncouple the magnet assembly and to drop to a closed position completing the full flush cycle.

Abstract: A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells.

Abstract: A system and method are disclosed for providing an electrically programmable read only memory (EPROM) in which each memory cell comprises an NMOS select transistor with a thick gate oxide and a PMOS breakdown transistor with a thin gate oxide. The source of the NMOS transistor and the source, drain and N well of the PMOS transistor are connected. The gate of the PMOS transistor is grounded. Under the control of the NMOS transistor, a programming voltage pulse is passed to the N well of the PMOS transistor of a selected memory cell. The magnitude of the voltage is sufficient to break the thin gate oxide of the PMOS transistor without damaging the NMOS transistor. Because the memory state of the memory cell depends on the breakdown status of the PMOS transistor, the data may be retained in the memory cell for an unlimited period of time.

Abstract: A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells.

Abstract: A system and method are disclosed for providing drain avalanche hot carrier (DAHC) programming for non-volatile memory (NVM) applications. A memory cell of the present invention comprises a program transistor and a control capacitor, each having a gate coupled together to form a floating gate. The size of the program transistor is selected to create a coupling ratio between the program transistor and the control capacitor that is large enough to facilitate a Fowler-Nordheim erase process and small enough to facilitate DACH programming. A source bias voltage is supplied to the source of the program transistor to increase the hot electron injection rate and to decrease the hot electron generation rate in the memory cell.

Abstract: A system and method is disclosed for providing a CMOS compatible single poly electrically erasable programmable read only memory (EEPROM) with memory cells that comprise an NMOS program transistor. In a first embodiment the memory cells of the EEPROM comprise a PMOS control capacitor. In a second embodiment the memory cells of the EEPROM comprise an NMOS control capacitor. A well bias voltage is applied to the NMOS program transistor instead of a gate bias voltage. The well bias voltage enables the injection of (1) channel hot electrons, (2) second hot electrons initiated by the channel hot electrons, and (3) drain impact ionization hot electrons into a floating gate of the NMOS program transistor.

Abstract: The present invention provides a chain wear monitoring device for monitoring chain wear in a chain drive conveyor system. The chain wear monitor electronically measures, calculates, records, and reports the amount of chain wear along the entire length of the conveyor chain. The monitor calculates the wear as the number of inches per nominal ten foot section of chain. A large diameter measuring wheel is rotatably mounted on a shaft extending from the monitor control box. An encoder connected to the wheel is used measure the distance of the chain and a proximity sensor counts the links. A magnetic assembly may be fixed to the chain to cause the monitor to automatically start and stop a data recording session for a chain on a conveyor system at the same spot each time the chain is monitored, facilitating section by section comparison of chain wear.