Abstract: A power amplifier includes an array of transistors having outputs that are connected in parallel to one another and coupled to an output network. The power amplifier further includes digital circuitry, configured to receive a sequence of control words that specify respective amplitudes of a signal to be transmitted in respective time intervals, and to transmit the signal by performing, for each control word and respective time interval: partitioning the control word into a Least Significant Bit (LSB) portion and a Most Significant Bit (MSB) portion; selecting a time duration based on the LSB portion; selecting an amplitude based on the MSB portion; and activating the array of transistors during the time interval in accordance with the selected time duration and the selected amplitude.

Abstract: A method of adjusting signal processing in a receiver based on signal strength includes determining a received signal strength indicator (RSSI) level, defining an RSSI value to be high when the RSSI level is above a first threshold or defining the RSSI value to be low when the RSSI level is below the first threshold, determining an automatic gain control (AGC) gain level, defining an AGC value to be high when the AGC gain level is above a second threshold or defining the AGC value to be low when the AGC gain level is below the second threshold, and adjusting power consumption of one or more receiver stages based on the RSSI value and the AGC value.

Abstract: Devices and systems for providing reduced cost and increased reliability power line communications (PLC) and electrical power to a network device using a PLC supply unit via a single cable with 2 wires are disclosed. The PLC supply unit receives a PLC power and data signal, extracts the power signal, the data signal and generates a timing signal based on the power signal. The PLC supply converts the electrical power signal from an alternating current (AC) to a direct current (DC) electrical power signal and then recombines the DC electrical power signal with the data signal and the timing signal and sends the composite signal to the network device. The network device receives the composite signal and uses the DC electrical power signal to power the network device and, at an internal PLC processing module, processes the data signal for communication with other network devices using the timing data.

Abstract: An apparatus includes a signal converter configured to convert a voltage signal into a current signal and an analog digital converter (ADC) configured to convert the current signal to a digital signal. The apparatus also includes a digital processor configured to process the digital signal and generate an output signal that indicates a zero crossing point of the mains voltage signal.

Abstract: In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: An apparatus includes a signal converter configured to convert a voltage signal into a current signal and an analog digital converter (ADC) configured to convert the current signal to a digital signal. The apparatus also includes a digital processor configured to process the digital signal and generate an output signal that indicates a zero crossing point of the mains voltage signal.

Abstract: In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: A system includes a weighting module, a mixer module, and a frequency selective impedance (FSI). The weighting module is configured to receive an input signal having an amplitude and to generate weighted outputs. Amplitudes of the weighted outputs have ratios relative to the amplitude of the input signal. The mixer module has switches configured to receive the weighted outputs and to generate a staircase waveform when the switches are clocked by clock signals. Amplitudes of steps of the staircase waveform are based on the ratios. The FSI is configured to communicate with the switches. The switches are configured to translate an impedance of the FSI centered on a first frequency to a second frequency determined by a frequency of the clock signals.

Abstract: A controller in a receiver monitors RSSI and AGC gain levels to determine signal conditions and adjust filter performance accordingly to optimize power consumption while providing acceptable signal quality. When RSSI level is high and AGC gain is low, a strong signal-of-interest is present. In this case, adaptive filter bias currents may be reduced raise the noise floor and degrade intermodulation to reduce power consumption because the strong signal-of-interest can tolerate the higher noise and distortion. When the RSSI level is low and AGC gain is high, a weak signal is present a low noise mode may be effected by increasing bias current to filters used to lower the noise floor, but intermodulation effects may still be tolerated so those filters may be cut back. Other cases are supported. RSSI and AGC gain level thresholds may be dynamically altered based on relative RSSI and AGC levels.

Abstract: A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.

Abstract: In one embodiment, the present invention includes noise reduction circuits and methods. In one embodiment, cross coupled switching transistors incorporate bias voltages between the control terminal of each transistor and the drain of the other transistor. The bias voltages increase the voltage on each transistors drain terminal and reduce noise upconversion in the system. In one embodiment, the source voltages of each transistor may be increased to linearize the circuit and further reduce noise. In another embodiment, a current is coupled to a PN junction to generate a low noise bias voltage. The bias voltage is used to bias capacitors of a selectively activated and deactivated capacitance to reduce noise. Features and advantages of the present invention may be implemented in an oscillator circuit, which may be used in a communication system, for example.

Abstract: A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Abstract: A phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal. The phase-locked loop may include a VCO with an LC tank circuit, the capacitance of which may be adjusted in incremental units. By gradually adjusting a control signal applied to a selected VCO LC tank circuit frequency adjustment control line, e.g., in a continuous ramped function, or time-averaged ramped function, from LOW-to-HIGH or from HIGH-to-LOW, over a period of time that is greater than the response time of the phase-locked loop, a frequency range supported by the VCO may be shifted to either a higher frequency range or a lower frequency range, as needed, to accommodate environmentally induced frequency drift in the VCO, without introducing noise or discontinuities in the frequency of the generated phase-locked loop output signal.

Abstract: Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.

Abstract: A body switch system includes a timing module that generates a plurality of clock signals, an input node that receives an input signal, an output node that transmits an output signal; and a body switch circuit that selectively couples a body of a first transistor of a plurality of transistors to one of the input node and the output node and a body of a second transistor of the plurality of transistors to the other one of the input node and the output node based on the plurality of clock signals.

Abstract: A radio frequency (RF) receiver includes an intermediate frequency (IF) mixer that generates an output signal based on mixing a hybrid in-band, on-channel (IBOC) signal with an intermediate frequency signal. An oscillator generates the intermediate frequency signal; wherein the intermediate frequency is less than a bandwidth of the IBOC signal.

Abstract: A phase mismatch compensation system includes a first summer that has a first input that communicates with a first phase of a received signal and an output. A second summer has a first input that communicates with a second phase of the received signal and an output, wherein the second phase is offset from the first phase. A first filter selectively filters the output of the first summer. An adaptive control module determines a predicted shift between the first and second phases of the received signal based on an output of the first filter and an actual shift between the first and second phases of the received signal. A correction module communicates with an output of the adaptive control module and the first phase and second phase of the received signal. The correction module outputs a mismatch correction to second inputs of the first and second summers respectively.