Patents by Inventor David Cowperthwaite
David Cowperthwaite has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230306552Abstract: Described herein is a partitional graphics processor including a display controller including hardware display virtualization. One embodiment provides a graphics processor comprising a system interface including a first virtual interface and a second virtual interface, a render engine to perform graphics rendering operations, and a display engine including hardware display virtualization. The render engine is configured to perform a first rendering operation in response to a command received via the first virtual interface and a second rendering operation in response to a command received via the second virtual interface. The display engine configured to present output of the first rendering operation via a first physical display plane that is associated with the first virtual interface and present output of the second rendering operation via a second physical display plane that is associated with the second virtual interface.Type: ApplicationFiled: May 27, 2022Publication date: September 28, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, David Puffer, Ankur Shah, Alan Previn Teres Alexis, Satyeshwar Singh
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Publication number: 20230298129Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.Type: ApplicationFiled: June 24, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, David Cowperthwaite, Aditya Navale
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Publication number: 20230297440Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Jeffery S. Boles, Hema Chand Nalluri, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala
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Publication number: 20230298128Abstract: Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table.Type: ApplicationFiled: June 24, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Puffer, Ankur Shah, Niranjan Cooray, Aditya Navale, David Cowperthwaite
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Publication number: 20230298125Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Hema Chand Nalluri, Jeffery S. Boles, David Cowperthwaite, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Vasanth Ranganathan, Joydeep Ray, David Puffer, Ankur Shah, Vidhya Krishnan, Kritika Bala, Aravindh Anantaraman, Michael Apodaca, Kenneth Daxer
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Publication number: 20230297421Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.Type: ApplicationFiled: May 27, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: David Cowperthwaite, Kenneth Daxer, Aditya Navale, Prasoonkumar Surti, Arthur Hunter, Hema Chand Nalluri, Jeffery S. Boles, Vasanth Ranganathan, Joydeep Ray, David Puffer, Aravindh Anantaraman, Ankur Shah, Vidhya Krishnan, Kritika Bala, Michael Apodaca
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Patent number: 11354171Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.Type: GrantFiled: December 22, 2020Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Prasoonkumar Surti, David Cowperthwaite, Abhishek R. Appu, Joydeep Ray, Vasanth Ranganathan, Altug Koker, Balaji Vembu
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Publication number: 20220138286Abstract: Systems, apparatuses and methods may provide for encryption based technology. Data may be encrypted locally with a graphics processor with encryption engines. The graphics processor components may be verified with a root-of-trust and based on collection of claims. The graphics processor may further be able to modify encrypted data from a non-pageable format to a pageable format. The graphics processor may further process data associated with a virtual machine based on a key that is known by the virtual machine and the graphics processor.Type: ApplicationFiled: December 23, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: David Zage, Scott Janus, Ned M. Smith, Vidhya Krishnan, Siddhartha Chhabra, Rajesh Poornachandran, Tomer Levy, Julien Carreno, Ankur Shah, Ronald Silvas, Aravindh Anantaraman, David Puffer, Vedvyas Shanbhogue, David Cowperthwaite, Aditya Navale, Omer Ben-Shalom, Alex Nayshtut, Xiaoyu Ruan
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Publication number: 20210263755Abstract: Apparatus and method for implementing a virtual display. For example, one embodiment of a graphics processing apparatus comprises at least one configuration register to store framebuffer descriptor information for a first guest running on a first virtual machine (VM) in a virtualized execution environment of a host processor, the framebuffer descriptor information to indicate one or more display pipes assigned to the first guest; and execution circuitry to execute a first driver assigned to the first guest, the first guest to use the first driver to display a framebuffer in a plane associated with one of the display pipes in accordance with the framebuffer descriptor information.Type: ApplicationFiled: November 30, 2018Publication date: August 26, 2021Inventors: Kun TIAN, Ankur SHAH, David COWPERTHWAITE, Zhi WANG, Zhenyu WANG, Kalyan KONDAPALLY, Jonathan BLOOMFIELD, Wei ZHANG
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Publication number: 20210182120Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.Type: ApplicationFiled: December 22, 2020Publication date: June 17, 2021Applicant: Intel CorporationInventors: Prasoonkumar Surti, David Cowperthwaite, Abhishek R. Appu, Joydeep Ray, Vasanth Ranganathan, Altug Koker, Balaji Vembu
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Patent number: 10877815Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.Type: GrantFiled: November 26, 2019Date of Patent: December 29, 2020Assignee: INTEL CORPORATIONInventors: Prasoonkumar Surti, David Cowperthwaite, Abhishek R. Appu, Joydeep Ray, Vasanth Ranganathan, Altug Koker, Balaji Vembu
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Publication number: 20200210246Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.Type: ApplicationFiled: November 26, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: PRASOONKUMAR SURTI, DAVID COWPERTHWAITE, ABHISHEK R. APPU, JOYDEEP RAY, VASANTH RANGANATHAN, ALTUG KOKER, BALAJI VEMBU
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Publication number: 20180082465Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.Type: ApplicationFiled: September 16, 2016Publication date: March 22, 2018Inventors: PRASOONKUMAR SURTI, TOMAS G. AKENINE-MOLLER, DAVID COWPERTHWAITE, KEVIN TIAN, PETER L. DOYLE, BRENT INSKO, ADAM T. LAKE
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Publication number: 20080063262Abstract: A method for processing data includes identifying a time signature of an infra-red (IR) beacon. Image data associated with the IR beacon is identified using the time signature.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Inventors: David Cowperthwaite, Bradford Needham
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Publication number: 20060214951Abstract: An improved method for display of a transitional region of interest while transitioning between a first region of interest and a second region of interest within visual information on a display screen of a computer. The method comprising the steps of applying a transitional transformation to the visual information and displaying the transitional transformed visual information on the display screen. The transitional transformation requiring a reduced calculation for transforming the visual information in the transitional region.Type: ApplicationFiled: June 1, 2006Publication date: September 28, 2006Inventors: David Baar, David Cowperthwaite, Mark Tigges
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Publication number: 20050210158Abstract: A method, apparatus and system are described for seamlessly and concurrently sharing a graphics device amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, a graphics device may be shared by multiple VMs such that only the output of one VM (i.e., the “focus VM”) is displayed on a display device coupled to the host computer. The focus VM may be identified according to a variety of ways. The focus VM may render its output into a frame-buffer and/or an overlay buffer, and the page table entries (“PTEs) that point to the frame-buffer may then be copied to a display buffer in an unused memory location associated with the focus VM. The PTEs may additionally be copied to display buffers in unused memory locations associated with the non-focus VMs on the host. The display buffer may then output its display (via the pointers to the frame buffers) to the display device.Type: ApplicationFiled: March 5, 2004Publication date: September 22, 2005Inventors: David Cowperthwaite, Michael Goldsmith, Kiran Panesar
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Publication number: 20050198633Abstract: A method, apparatus and system are described for seamlessly sharing I/O devices amongst multiple virtual machines (“VMs”) on a host computer. Specifically, according to one embodiment of the invention, the virtual machine manager (“VMM”) on the host cycles access to the I/O devices amongst the VMs according to a round robin or other such allocation scheme. In order to provide direct access to the devices, the VMM may save the device state pertaining to the currently active VM, store the state in a memory region allocated to the currently active VM, retrieve a device state for a new VM from its memory region and restore the device using the retrieved device state, thus providing the illusion that each VM has direct, full-speed, exclusive access to the I/O device.Type: ApplicationFiled: March 5, 2004Publication date: September 8, 2005Inventors: Philip Lantz, Michael Goldsmith, David Cowperthwaite, Kiran Panesar
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Publication number: 20050198632Abstract: A method, apparatus and system enable a virtual machine manager (“VMM”) to dynamically reassign physical devices from one virtual machine (“VM”) to another. The VMM may generate a message to the VM that currently owns the physical device and inform the device that the physical device is shutting down. The current VM may thereafter idle the physical device, unload the device driver and eject the device. The VMM may then inform another VM that the physical device is available, and the second VM may load the driver for the device.Type: ApplicationFiled: March 5, 2004Publication date: September 8, 2005Inventors: Philip Lantz, Michael Goldsmith, David Cowperthwaite
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Publication number: 20050041046Abstract: A method for displaying visual information on a display screen of a computer, comprising the steps of scaling the visual information to produce a scaled representation to fit on the display screen the scaled representation containing the entire content of the visual information; selecting a region of interest within the scaled representation; applying a transformation to the scaled representation to improve the visual detail in the region of interest; and, displaying the transformed presentation on the display screen.Type: ApplicationFiled: June 2, 2004Publication date: February 24, 2005Inventors: David Baar, M. Sheelagh Carpendale, David Cowperthwaite, Mark Tigges, Robert Komar, Jerome Bauer
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Publication number: 20040257375Abstract: In a data processing system that executes a program of instructions, a method for generating a detail-in-context presentation of a three-dimensional information representation comprising the steps of selecting a object-of-interest in the information representation; selecting a viewpoint; selecting a path from the viewpoint to the object-of-interest; and, displacing objects in the information representation away from the path to locations within the information representation where the objects remain visible when viewed from the viewpoint yet do not occlude the object-of-interest when viewed from the viewpoint to thereby generate the detail in context view.Type: ApplicationFiled: July 7, 2004Publication date: December 23, 2004Inventor: David Cowperthwaite