Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

Abstract: A bipolar transverse flux electric motor that is configured to produce a uniform distribution of alternating magnetic fields through utilization of a specific stator and a first coil and a second coil. The bipolar transverse flux electric motor includes a first coil and a second coil wherein the first coil and second coil are positioned in a side by side configuration and wherein the first coil and second coil are have a current flow in opposing directions. The plurality of stators have a shape that includes upper portion and a lower portion with an internal void. The upper portion is greater in width that the lower portion and the lower portion includes two members configured to create a step form. The step form of the lower portion is configured to facilitate the inverse positioning of the stators so as to provide magnetic fields in opposing directions for adjacent stators.

Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.

Abstract: A method of maintaining a device table cache (DTC) included in a Synchronous input/output (I/O) computing system includes issuing, with a processor executing an operating system running on the Synchronous I/O computing system, a Synchronous I/O command indicating a request to perform a device table entry transaction including a plurality of device table entries. The method also includes determining, with a host bridge processor, based on device table information, whether the device table entry transaction is associated with a cyclic redundancy check (CRC) transaction, and pinning, with the host bridge processor, a device table entry from a device table based on the determination.

Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.

Abstract: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block.

Abstract: Error checking in a computing environment at an input/output (I/O) level is facilitated by associating a cyclic redundancy check (CRC) control element (CCE) with an input/output (I/O) operation based on a command to perform the I/O operation of the computing environment. The CRC control element is used in accumulating during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the I/O operation. By way of example, the associating and the accumulating of the accumulated CRC value may be performed within an I/O hub of the computing environment, and where data of the I/O operation is transferred in data fragments, the CRC control element is updated for each data fragment during the accumulating of the CRC context for the I/O operation.

Abstract: Error-handling in a computing environment at an input/output (I/O) level is facilitated by associating a control element with an input/output (I/O) operation based on a command to perform the I/O operation between an adapter and memory. Based on detection of an error for the I/O operation, the control element is updated to indicate an error state, and completion of any uncompleted I/O request for the I/O operation is blocked, while other I/O requests for one or more other I/O operations are allowed to proceed between the adapter (or adapter function) and the memory. By way of example, the control element may be a cyclic redundancy check (CRC) control element used, for instance, by an I/O hub of the computing environment to accumulate during performance of the I/O operation an accumulated CRC value for the I/O operation to facilitate error checking of the operation.

Abstract: An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This access is via instructions implemented based on the architecture of the adapter function. The host also has the capability to intervene in the execution of the instruction, if desired.

Abstract: An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available.

Abstract: A plurality of address spaces are assigned to an adapter. To select a particular address space for the adapter, a requestor identifier and address space identifier provided in a request by the adapter are used. Each address space may have a different address translation mechanism associated therewith.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.

Abstract: Embodiments are directed to a method and a computer program product for extending a page table. In an embodiment, the method comprises receiving, by a host bridge, a request. The method further comprises determining, by the host bridge, that access to a memory address space referenced by the request is authorized based on a requester identifier associated with the request. Based on determining that access to the memory address space is authorized, the method comprises accessing, by the host bridge, a page included in the memory address space based on a combination of: a start of the page table and a single extended index.

Abstract: An extension of a page table is provided. An aspect includes receiving, by a host bridge, a request. An aspect includes determining, by the host bridge, that access to a memory address space referenced by the request is authorized based on a requester identifier associated with the request. An aspect includes, based on determining that access to the memory address space is authorized, accessing, by the host bridge, a page included in the memory address space based on a combination of: a start of the page table and a single extended index.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.