Patents by Inventor David Cureton Baker
David Cureton Baker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079081Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth long distance communication, e.g. photonic or electronic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.Type: ApplicationFiled: September 29, 2023Publication date: March 7, 2024Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
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Publication number: 20240078175Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.Type: ApplicationFiled: January 13, 2023Publication date: March 7, 2024Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
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Publication number: 20240077781Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication and augment existing memory systems to allow them to be both high capacity and high bandwidth simultaneously.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Inventors: Mitchell A NAHMIAS, Michael J. HOCHBERG, Thomas W. BAEHR-JONES, Ari NOVACK, David Cureton BAKER, Matthew CHANG, Lei WANG, Matthew STRESHINSKY, Wuchun WU, Hamidreza NAHAVANDI, Brian West
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Publication number: 20240078016Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication.Type: ApplicationFiled: December 30, 2022Publication date: March 7, 2024Inventors: David Cureton BAKER, Ari NOVACK, Donovan POPPS, Benjamin Wiley MELTON, Bryan COPE, Mark BAUR, Anahita SHAYESTEH
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Patent number: 10951212Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.Type: GrantFiled: February 7, 2019Date of Patent: March 16, 2021Assignee: Eta Compute, Inc.Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
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Patent number: 10578656Abstract: An energy consumption monitor for use in an electronic system comprising an integrated circuit such as a microcontroller. The monitor comprises a counter adapted to accumulate pulses developed by a charge source, each pulse indicative of the delivery of one unit of charge to a load circuit. A monitoring facility monitors the counter to develop an energy consumption record over time.Type: GrantFiled: October 20, 2015Date of Patent: March 3, 2020Assignee: Ambiq Micro, Inc.Inventors: Scott Hanson, Stephen James Sheafor, David Cureton Baker
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Publication number: 20190190520Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
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Patent number: 10205453Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.Type: GrantFiled: April 9, 2018Date of Patent: February 12, 2019Assignee: Eta Compute, Inc.Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
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Publication number: 20180294810Abstract: There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.Type: ApplicationFiled: April 9, 2018Publication date: October 11, 2018Inventors: Chao Xu, Gopal Raghavan, Ben Wiley Melton, Vidura Manu Wijayasekara, Bryan Garnett Cope, David Cureton Baker, John Whitaker Havlicek
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Patent number: 10025557Abstract: An 8×8 binary digital multiplier reduces the height of partial product columns to be no more than 7 bits high. The six 7-bit high middle columns are each input to a (7:3) counter. An ascending triangle compressor operates on the lesser significant bit columns. A descending triangle compressor operates on the greater significant bit columns. The counter and compressor outputs are combined for a final stage of compression, followed by partial product addition.Type: GrantFiled: December 5, 2015Date of Patent: July 17, 2018Assignee: Firefly DSP LLCInventors: Craig Franklin, David Cureton Baker
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Publication number: 20170161021Abstract: An 8×8 binary digital multiplier reduces the height of partial product columns to be no more than 7 bits high. The six 7-bit high middle columns are each input to a (7:3) counter. An ascending triangle compressor operates on the lesser significant bit columns. A descending triangle compressor operates on the greater significant bit columns. The counter and compressor outputs are combined for a final stage of compression, followed by partial product addition.Type: ApplicationFiled: December 5, 2015Publication date: June 8, 2017Applicant: Firefly DSP LLCInventors: Craig Franklin, David Cureton Baker
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Publication number: 20160109494Abstract: An energy consumption monitor for use in an electronic system comprising an integrated circuit such as a microcontroller. The monitor comprises a counter adapted to accumulate pulses developed by a charge source, each pulse indicative of the delivery of one unit of charge to a load circuit. A monitoring facility monitors the counter to develop an energy consumption record over time.Type: ApplicationFiled: October 20, 2015Publication date: April 21, 2016Applicant: AMBIQ MICRO, INC.Inventors: Scott Hanson, Stephen James Sheafor, David Cureton Baker
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Patent number: 8639946Abstract: The disclosure includes a system and method of using a processor and protected memory. In a particular embodiment, the system includes a processor, a volatile memory accessible to the processor, and a first nonvolatile memory accessible to the processor. The first nonvolatile memory includes a first portion of memory that is protected and is readable when a shield bit indicates an unshielded mode of operation, but is unreadable when the shield bit indicates a shielded mode of operation and a second portion of memory that is unprotected and that is readable regardless of the value of the shield bit. The system includes a second nonvolatile memory including data to be transferred to the volatile memory.Type: GrantFiled: June 24, 2005Date of Patent: January 28, 2014Assignee: Sigmatel, Inc.Inventor: David Cureton Baker
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Patent number: 7761773Abstract: A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of laser fuses represents error correction coding data that corresponds to the unique identifier. The unique identifier can be a digital rights management identification. Also, the error correction coding data is configured for use by a Reed-Solomon error correcting method to correct the unique identifier. Alternatively, the error correction coding data is configured for use by a cyclic redundancy check method.Type: GrantFiled: June 30, 2005Date of Patent: July 20, 2010Assignee: Sigmatel, Inc.Inventor: David Cureton Baker
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Patent number: 7657725Abstract: A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.Type: GrantFiled: June 24, 2005Date of Patent: February 2, 2010Assignee: Sigmatel, Inc.Inventor: David Cureton Baker
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Patent number: 7428603Abstract: The disclosure is directed to a device including a memory interface. The memory interface includes a data interface, a first state machine and a second state machine. The first state machine includes a first chip select interface and a first ready/busy interface. The first state machine is configured to select and monitor a first memory device via the first chip select interface and the first ready/busy interface, respectively, when the first memory device is coupled to the data interface. The second state machine includes a second chip select interface and a second ready/busy inter-face. The second state machine is configured to select and monitor a second memory device via the second chip select interface and the second ready/busy interface, respectively, when the second memory device is coupled to the data interface.Type: GrantFiled: June 30, 2005Date of Patent: September 23, 2008Assignee: Sigmatel, Inc.Inventors: Matthew Henson, David Cureton Baker
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Publication number: 20080189479Abstract: A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: SIGMATEL, INC.Inventors: Bryan Cope, Tauseef Rab, David Cureton Baker
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Patent number: 7409623Abstract: The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a data sector of the non-volatile computer memory. The first portion of the redundant memory area includes data associated with the data sector. The first portion of the redundant memory area includes a cyclic redundancy check code.Type: GrantFiled: November 4, 2004Date of Patent: August 5, 2008Assignee: Sigmatel, Inc.Inventors: David Cureton Baker, Grayson Dale Abbott, Josef Zeevi
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Patent number: 7397408Abstract: An analog-to-digital converter (ADC) system is disclosed and includes a programmable control register and a plurality of channels, each channel having an associated request bit within the programmable control register. The ADC system also includes a scheduler responsive to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the request bits are set. A method of scheduling analog-to-digital conversion is disclosed and includes receiving a request to schedule an analog-to-digital conversion for a channel of a plurality of channels. The method also includes scheduling an analog-to-digital conversion in response to receiving the request and performing the analog-to-digital conversion based on the request, where data that indicates the request is stored in a programmable control register.Type: GrantFiled: October 10, 2006Date of Patent: July 8, 2008Assignee: Sigmatel, Inc.Inventor: David Cureton Baker
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Patent number: 7376762Abstract: A system and method for providing direct memory access is disclosed. In a particular embodiment, a direct memory access module is disclosed that includes a memory, a first interface coupled to a processor, and a second interface coupled to a peripheral module. A first instruction received from the first interface is stored in the memory. The first instruction includes a number of programmed input/output words to be provided to the peripheral module via the second interface. The direct memory access module also includes an instruction execution unit to process the first instruction.Type: GrantFiled: October 31, 2005Date of Patent: May 20, 2008Assignee: SigmaTel, Inc.Inventors: Matthew Henson, David Cureton Baker