Abstract: An apparatus for brushing the hair of dogs and other animals. The apparatus comprises a hair brush with a depth guide that prevents the bristles from contacting the epidermis of the animal while its hair is brushed. Preventing the bristles from contacting the epidermis of the animal helps prevent injury and discomfort to the animal during grooming.

Abstract: An apparatus for brushing the hair of dogs and other animals. The apparatus comprises a hair brush with a depth guide that prevents the bristles from contacting the epidermis of the animal while its hair is brushed. Preventing the bristles from contacting the epidermis of the animal helps prevent injury and discomfort to the animal during grooming.

Abstract: A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: A method and reconfigurable computer architecture protect binary opcode, or other data and instructions by providing an encryption capability integrated into an instruction issue unit of a protected processor. Opcodes are encrypted at their source, and encrypted opcodes are then delivered to the CPU and decrypted “inside” the CPU. Access into the CPU is prevented. Each form of code or data selected for protection is protected from unauthorized viewing or access. Commonly, the binary executable, or object, code is selected for protection. However, protected information could also include source code or data sets or both. Encrypting opcodes will result in making unique opcodes for each processor. Encryption keys and hidden opcode algorithms provide further security.

Abstract: A method and apparatus for providing multiple layer encrypted Internet, Intranet, or e-mail communication device communications. In particular, the process of encrypting Internet, Intranet, or e-mail messages with encryption algorithms embedded in integrated circuits incorporated into the communication device, with access to the encrypting circuit requiring a validation of a randomly generated cypher key and an user defined password.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.

Abstract: A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).

Abstract: An apparatus is disclosed for improving the Single Event Latchup (SEL) performance of an integrated circuit device (IC), or grouping of devices (as an example Multi-Chip Modules or MCMs), through the addition of active electronic circuitry integrated within the IC or MCM package. This circuitry and the protected device can be incorporated within the same physical dimensions and electrical configuration as the original integrated circuit device. The circuitry turns a destructive Latchup of a device into a recoverable event, allowing electronic devices that where unsuitable for the space environment due to SEL to be useable in the space environment.

Abstract: The invention discloses a method for making two sided Multi-Chip Modules (MCMs) that will allow most commercially available integrated circuits to meet the thermal and radiation hazards of the spacecraft environment using integrated package shielding technology. The invention describes the technology and methodology to manufacture MCMs that are radiation-hardened, structurally and thermally stable using 3-dimensional techniques allowing for high density integrated circuit packaging in a radiation hardened package.

Abstract: This invention relates to 2-[(substituted)methylene]cephalosporin sulfones and in particular 2-[(heteroaryl substituted)methylene]cephalosporin sulfones which are effective elastase inhibitors as well as effective thrombin inhibitors and therefore are useful as anti-inflammatory, anti-degenerative and anti-thrombin agents.

Abstract: Derivatives of 2-spirocyclopropyl cephalosporin sulfone of the structural formula I ##STR1## are provided which are useful as potent elastase inhibitors.

Abstract: Derivatives of 2-spirocyclopropyl cephalosporin sulfone of the structural formula I ##STR1## are provided which are useful as potent elastase inhibitors.

Abstract: Derivatives of 2-spirocyclopropyl 4-acylcephem sulfones of the formula (I) ##STR1## are provided which are useful as potent elastase inhibitors and hence are useful in the prevention, control and treatment of inflammatory conditions, especially arthritis and emphysema.