Abstract: A source clock signal is received from a primary semiconductor device by a secondary semiconductor device via an interconnect. A local clock signal is generated on the secondary semiconductor device based on the source clock signal. A mode control signal is generated on the secondary semiconductor device, where the mode control signal indicates one of an unlock mode of operation and a lock mode of operation of the secondary semiconductor device. A physical interface (PHY) clock signal is generated based on the local clock signal, where the PHY clock signal includes the local clock signal during the lock mode, and the PHY clock signal includes an inverted version of the local clock signal during the unlock mode. Data received from the primary semiconductor device via the interconnect is latched at a positive edge of the PHY clock signal during the unlock mode and the lock mode.

Abstract: An integrated circuit is disclosed that includes a first signal line adjacent to a second signal line. A first latch is coupled between the first and second signal line. The first latch includes a first transistor having a first current electrode coupled to the first signal line and a control electrode coupled to the second control line and a second transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the first signal line. The first signal line typically runs substantially parallel to the second signal line. A signal generator circuit may be coupled to a first end of the first and second signal lines and a receiver circuit may be coupled to a second end of the first and second signal line. The first latch may be coupled closer to the second end of the first and second signal lines than the first end of the first and second signal lines.

Abstract: A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and waits until the data is requested again before it invalidates any cache aliased entries in the semi-associative cache array. This invalidation step requires no dedicated cycle but instead is a result of the memory cache being able to simultaneously read from the semi-associative cache array and the cache reload buffer.