Patents by Inventor David D. Eaton

David D. Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11392872
    Abstract: Methods, systems, and computer storage media are provided for optimizing workflows by monitoring a healthcare environment. Data may be compiled from various sources to monitor interactions within the healthcare environment. Both interactions with individuals and interactions with a healthcare system may be monitored. Each of location data, clinical data, and system data, among others, may be combined to monitor the healthcare environment. By combining the data from various sources, a user is able to get a complete picture of the healthcare environment.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 19, 2022
    Assignee: CERNER INNOVATION, INC.
    Inventors: David Compton, James D. Eaton, Jr., Matthew Gadzinski, Brannon Garvert, Mario Manese, Justin Nelson, David Pierre
  • Patent number: 9433067
    Abstract: A multi-lamp fluorescent light fixture includes a plurality of replaceable fluorescent lamp starter units. Each starter unit has a built-in microcontroller, an RF (Radio-Frequency) receiver, and communicates wirelessly with a master unit. The plurality of starter units can be wirelessly controlled to dim the multi-lamp fixture. Each starter unit receives a DIM command. Each starter unit identified as a dimmer starter unit responds to the DIM command by turning off coupled fluorescent lamps. Starter units not identified as dimmer starter units respond by leaving coupled lamps turned on, or alternatively, turning off and quickly restarting coupled lamps. Systems of existing light fixtures are retrofitted with such wireless starter units, and thereby made controllable by a master unit so that the master unit can dim the lights if room occupancy is not detected or if sufficient ambient light is available.
    Type: Grant
    Filed: October 3, 2009
    Date of Patent: August 30, 2016
    Assignee: IXYS Intl Limited
    Inventors: Kamlapati Khalsa, Yefim Gluzman, Quyen Tran, David D. Eaton
  • Patent number: 8198142
    Abstract: A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 12, 2012
    Assignee: IXYS CH GmbH
    Inventor: David D. Eaton
  • Publication number: 20110080107
    Abstract: A multi-lamp fluorescent light fixture includes a plurality of replaceable fluorescent lamp starter units. Each starter unit has a built-in microcontroller, an RF (Radio-Frequency) receiver, and communicates wirelessly with a master unit. The plurality of starter units can be wirelessly controlled to dim the multi-lamp fixture. Each starter unit receives a DIM command. Each starter unit identified as a dimmer starter unit responds to the DIM command by turning off coupled fluorescent lamps. Starter units not identified as dimmer starter units respond by leaving coupled lamps turned on, or alternatively, turning off and quickly restarting coupled lamps. Systems of existing light fixtures are retrofitted with such wireless starter units, and thereby made controllable by a master unit so that the master unit can dim the lights if room occupancy is not detected or if sufficient ambient light is available.
    Type: Application
    Filed: October 3, 2009
    Publication date: April 7, 2011
    Inventors: Kamlapati Khalsa, Yefim Gluzman, Quyen Tran, David D. Eaton
  • Patent number: 7898090
    Abstract: A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 1, 2011
    Assignee: IXYS CH GmbH
    Inventor: David D. Eaton
  • Patent number: 7868441
    Abstract: A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 11, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: David D. Eaton, David R. Staab, Ruben C. Zeta
  • Publication number: 20080251906
    Abstract: A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic.
    Type: Application
    Filed: May 3, 2007
    Publication date: October 16, 2008
    Inventors: David D. Eaton, David R. Staab, Ruben C. Zeta
  • Patent number: 6552410
    Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: April 22, 2003
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Ket-Chong Yap, Kevin K. Yee, E. Thomas Hart, Andrew K. Chan, Neal A. Palmer, Michael W. Dini, James Apland, Panawalge S. N. Gunaratna
  • Patent number: 6426649
    Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 30, 2002
    Assignee: QuickLogic Corporation
    Inventors: Robert Fu, David D. Eaton, Kevin K. Yee, Andrew K. Chan
  • Patent number: 6169416
    Abstract: The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected ones of those logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuses that are or may be selected for simultaneous programming from the other three logic regions.
    Type: Grant
    Filed: September 1, 1998
    Date of Patent: January 2, 2001
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Paige A. Kolze
  • Patent number: 6157207
    Abstract: To protect logic module output devices from high voltages, logic modules are not powered during antifuse programming. In some embodiments, two separate power input terminals VCC1 and VCC2 are provided: power input terminal VCC1 being coupled to power the logic modules, and power input terminal VCC2 being coupled to power the programming control circuitry. Power terminal VCC1 is left floating or is grounded during antifuse programming such that the logic modules are not powered but such that the programming circuitry is powered during antifuse programming via the second power terminal VCC2. Logic module output protection transistors are not required nor is the associated charge pump. Because the logic module input devices are not powered, a current surge through the input devices on power up does not occur and an internal disable signal and associated circuitry is not required.
    Type: Grant
    Filed: May 11, 1998
    Date of Patent: December 5, 2000
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Sudarshan Varshney, Paige A. Kolze
  • Patent number: 6140837
    Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 31, 2000
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Richard J. Wong, James M. Apland
  • Patent number: 6127845
    Abstract: In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.
    Type: Grant
    Filed: July 8, 1998
    Date of Patent: October 3, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, Andre Stolmeijer, David D. Eaton
  • Patent number: 5986469
    Abstract: A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: November 16, 1999
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Paige A. Kolze, James M. Apland
  • Patent number: 5898776
    Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: April 27, 1999
    Assignee: QuickLogic Corporation
    Inventors: James M. Apland, David D. Eaton, Andrew K. Chan
  • Patent number: 5892370
    Abstract: A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.
    Type: Grant
    Filed: January 3, 1997
    Date of Patent: April 6, 1999
    Assignee: QuickLogic Corporation
    Inventors: David D. Eaton, Mukesh T. Lulla, Ker-Ching Liu