Abstract: A free-from radio frequency (RF) media includes a substrate having a first dielectric layer formed thereon and a second dielectric layer on an upper surface of the first dielectric layer. A first conductive layer is formed on an upper surface of the first dielectric layer and has a first overall profile. A second conductive layer having a second overall profile is formed on an upper surface of the second dielectric layer such that the second dielectric layer is interposed between the first and second conductive layers. The first overall profile of the first conductive layer is different from the second overall profile of the second conductive layer.

Abstract: A free-from radio frequency (RF) media includes a substrate having a first dielectric layer formed thereon and a second dielectric layer on an upper surface of the first dielectric layer. A first conductive layer is formed on an upper surface of the first dielectric layer and has a first overall profile. A second conductive layer having a second overall profile is formed on an upper surface of the second dielectric layer such that the second dielectric layer is interposed between the first and second conductive layers. The first overall profile of the first conductive layer is different from the second overall profile of the second conductive layer.

Abstract: An HPA MMIC assembly includes a MMIC device coupled to a thermal spreader. A ground plane is provided on the thermal spreader and coupled to FETs in the MMIC device. The multiple levels of metal separated by multiple dielectric layers provide low-loss broad-band microstrip circuits. The thermal spreader may include diamond, an air/wire-edm spreader or a multi-layer board (MLB) with heat sink vias and ground vias.

Abstract: An HPA MMIC assembly includes a MMIC device coupled to a thermal spreader. A ground plane is provided on the thermal spreader and coupled to FETs in the MMIC device. The multiple levels of metal separated by multiple dielectric layers provide low-loss broad-band microstrip circuits. The thermal spreader may include diamond, an air/wire-edm spreader or a multi-layer board (MLB) with heat sink vias and ground vias.

Abstract: Guanella topology balun/unun impedance transformer contains cascaded, i.e., series-coupled, coils of different sizes implemented in RF CMOS technology. The cascading of differently-sized coils provides for a large resonance-free operating bandwidth. The shunt inductive loading maximizes low frequency performance.

Abstract: Guanella topology balun/unun impedance transformer contains cascaded, i.e., series-coupled, coils of different sizes implemented in RF CMOS technology. The cascading of differently-sized coils provides for a large resonance-free operating bandwidth. The shunt inductive loading maximizes low frequency performance.

Abstract: A switchable charge pump (SCP) combines a switching element and a charge pump. An SCP can be utilized within an RF circuit to allow the charge pump to be activated or deactivated in the circuit depending on incident RF power level. Multiple SCPs can be utilized to provide a generalized a single-pole N-throw (SPNT) system architecture. In one example, an RF transmit-receive (T/R) system utilizes SCPs to operate in one of three modes: transmit mode, receive mode, or self-selecting terminate mode.

Abstract: A switchable charge pump (SCP) combines a switching element and a charge pump. An SCP can be utilized within an RF circuit to allow the charge pump to be activated or deactivated in the circuit depending on incident RF power level. Multiple SCPs can be utilized to provide a generalized a single-pole N-throw (SPNT) system architecture. In one example, an RF transmit-receive (T/R) system utilizes SCPs to operate in one of three modes: transmit mode, receive mode, or self-selecting terminate mode.

Abstract: A circuit for amplifying a source signal generated by a signal source having a first impedance includes a transmission line transformer (TLT) having a first, a second, a third, and a fourth port wherein the TLT is coupled to receive the source signal at the first port and configured to output a corresponding impedance matched signal at the second port, the second port is coupled to the third port of the TLT, the circuit also including a TLT load having a first terminal coupled to the fourth port of the TLT and a second terminal coupled to a reference potential. The circuit additionally includes an amplifier device responsive to the impedance matched signal to generate an amplified signal.

Abstract: A circuit for amplifying a source signal generated by a signal source having a first impedance includes a transmission line transformer (TLT) having a first, a second, a third, and a fourth port wherein the TLT is coupled to receive the source signal at the first port and configured to output a corresponding impedance matched signal at the second port, the second port is coupled to the third port of the TLT, the circuit also including a TLT load having a first terminal coupled to the fourth port of the TLT and a second terminal coupled to a reference potential. The circuit additionally includes an amplifier device responsive to the impedance matched signal to generate an amplified signal.

Abstract: Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.

Abstract: Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.

Abstract: A bias circuit includes second order process variation compensation in a current source topology having a compensation transistor operating in saturation mode as a current source. An additional compensation transistor is biased to operate in a linear mode to provide an active resistor to vary a control voltage applied to the saturation mode compensation transistor and widen the range of sourced control current, thus widening the achievable range of the control voltage applied to the biasing transistor to produce a predetermined level of bias current despite process variations. The additional compensation transistor has been shown to be able to compensate for another approximately 20-25% of the induced variations leaving less than approximately 10% and preferably less than 5% variation in the bias current from the predetermined level at certain bias conditions and over typical fabrication process variations.

Abstract: A temperature control system having: a resistor formed in a region of a semiconductor, such resistor having a pair of spaced electrodes in ohmic contact with the semiconductor; at least one device formed in another region of the semiconductor thermally proximate the resistor formed region, such device generating heat in the semiconductor; and circuitry, including a reference connected to one of the pair of electrodes, for operating the resistor in saturation and for sensing variation in the resistor in response to the heat generated by the device and for controlling the heat generated by the device in the semiconductor in response to the sensed variation.

Abstract: A temperature control system having: a resistor formed in a region of a semiconductor, such resistor having a pair of spaced electrodes in ohmic contact with the semiconductor; at least one device formed in another region of the semiconductor thermally proximate the resistor formed region, such device generating heat in the semiconductor; and circuitry, including a reference connected to one of the pair of electrodes, for operating the resistor in saturation and for sensing variation in the resistor in response to the heat generated by the device and for controlling the heat generated by the device in the semiconductor in response to the sensed variation.

Abstract: The present invention relates to microwave circuits, and more particularly to bypass circuits for bias connections. The bypass circuit comprises a capacitor in series with an inductor, the series combination being connected between the bias conductor and ground. This series combination provides low return loss at the operating frequency. A de-queueing circuit may be included in the bypass circuit to provide loss at other frequencies.

Abstract: The present invention relates to microwave circuits, and more particularly to bypass circuits for bias connections. The bypass circuit comprises a capacitor in series with an inductor, the series combination being connected between the bias conductor and ground. This series combination provides low return loss at the operating frequency. A de-queueing circuit may be included in the bypass circuit to provide loss at other frequencies.

Abstract: An amplifier including an amplifier transistor, and a switch transistor, wherein the amplifier is configured to be switched on and off by controlling bias voltages of the transistors.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: According to one embodiment of the invention a method for switching an alternating current signal between at least two paths includes providing, in at least one of the paths, first and second field effect transistors in series. The method also includes providing a control voltage node operable to receive a control voltage and maintaining each of the first and second field effect transistors in pinch-off mode by offsetting a voltage on each gate of the field effect transistors with a DC voltage component other than the control voltage when it is desired for the alternating current not to flow through the at least one path.