Patents by Inventor David D. R. Chevrie

David D. R. Chevrie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8283750
    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: October 9, 2012
    Assignee: IPDIA
    Inventors: Lionel Guiraud, Francois Lecornec, Johan H. Klootwijk, Freddy Roozeboom, David D. R. Chevrie
  • Patent number: 7982558
    Abstract: Method of manufacturing a MEMS device integrated in a silicon substrate. In parallel to the manufacturing of the MEMS device passive components as trench capacitors with a high capacitance density can be processed. The method is especially suited for MEMS resonators with resonance frequencies in the range of 10 MHz.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: July 19, 2011
    Assignee: NXP B.V.
    Inventors: Marc Sworowski, David D. R. Chevrie, Pascal Philippe
  • Publication number: 20100230787
    Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.
    Type: Application
    Filed: April 30, 2007
    Publication date: September 16, 2010
    Applicant: NXP B.V.
    Inventors: Lionel Guiraud, Francois Lecornec, Johan H. Klootwijk, Freddy Roozeboom, David D. R. Chevrie
  • Patent number: 7786014
    Abstract: The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206? from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218? from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: August 31, 2010
    Assignee: IPDIA
    Inventors: Francois Neuilly, David D. R. Chevrie, Dominique Yon
  • Publication number: 20090269931
    Abstract: The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206? from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218? from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.
    Type: Application
    Filed: September 14, 2007
    Publication date: October 29, 2009
    Applicant: NXP, B.V.
    Inventors: Francois Neuilly, David D. R. Chevrie, Dominique Yon