Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: Embodiments include methods and apparatus for wireless network communication between a device that operates a radio in compliance with a wireless communication standard and another device that may not be capable of complying with the wireless communication standard. In an embodiment the non-complaint device is a receiver only. Information is broadcast or advertised or otherwise transmitted by the compliant device according to the protocol and embodiments encode information on top of the protocol for decoding by the receiving device, which does not decode the protocol.

Abstract: An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.

Abstract: A quadrature fully integrated tri-band GPS receiver implemented in 65 nm CMOS. The analog front-end (AFE) is specifically designed for a miniaturized low-power GPS logger that leverages heavy duty-cycling. The main contribution of the RF front-end is comprised of two main signal paths which support the single-band only mode and the tri-band mode (L1, L2, L5). In the tri-band mode, the AFE is able to fold three GPS signals into a single low intermediate frequency channel in part due to the orthogonality of the pseudo-ransom codes. In active mode, the radio draws 12.1 mW in the single-band (L1) mode with a LNA and an active mixer, and 8.2 mW in the tri-band mode with a passive front-end, from a 1.2V supply, and with a startup time of 20 us.

Abstract: A digital quadrature architecture is presented that employs switched current digital power amplifiers and uses a digital class-B input code profile in combination with non-overlapping LO signals to overcome the low efficiency problems of conventional quadrature architectures. By employing digital class-B signals, the number of I/Q cells is reduced to half and the need for extra processing of the sign bits is eliminated in the transmitters, thereby improving the efficiency.

Abstract: In some embodiments, an apparatus includes an integrated circuit such as a system on chip that operates in part from harvested power and that uses information about power harvesting conditions to alter a power-on sequence or boot sequence based on that information. In some embodiments, a method uses information about power harvesting and energy harvesting conditions to alter a power-on sequence or boot sequence.

Abstract: A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

Abstract: In some embodiments, an apparatus includes an integrated circuit such as a system on chip that operates in part from harvested power and that uses information about power harvesting conditions to alter a power-on sequence or boot sequence based on that information. In some embodiments, a method uses information about power harvesting and energy harvesting conditions to alter a power-on sequence or boot sequence.

Abstract: An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.

Abstract: An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.

Abstract: An integrated ultra wideband transceiver. The transceiver comprises a transmitter, a receiver, and at least one on-chip monopole antenna electrically connected to at least one of the transmitter or receiver for transmitting and/or receiving electrical signals. The transceiver further comprises a clock generator comprising a temperature-compensated relaxation oscillator, a baseband controller electrically connected to, and configured to exert a measure of control over, at least one the transmitter, receiver, or clock generator, and a micro-battery operative to provide operating power to each of the transmitter, receiver, clock generator, and baseband controller.

Abstract: A low power long range transceiver is presented. The transceiver includes: an antenna configured to receive an RF signal; an analog front-end circuit configured to receive the RF signal from the antenna and pre-condition the RF signal by at least one of amplify the RF signal, shift frequency of the RF signal and filter the RF signal; and a demodulator configured to receive the preconditioned signal from the front-end circuit and an assertion trigger signal signifying an end of a predefined time period, where the demodulator, in response to the assertion trigger signal, outputs a data value for a given data bit in the RF signal. A controller is also configured to receive the assertion trigger signal and, in response to the assertion trigger signal, disables at least one component of the transceiver, thereby reducing power consumption.

Abstract: A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.

Abstract: In some embodiments, an apparatus includes an integrated circuit such as a system on chip that operates in part from harvested power and that uses information about power harvesting conditions to alter a power-on sequence or boot sequence based on that information. In some embodiments, a method uses information about power harvesting and energy harvesting conditions to alter a power-on sequence or boot sequence.

Abstract: Embodiments include methods and apparatus for wireless network communication between a device that operates a radio in compliance with a wireless communication standard and another device that may not be capable of complying with the wireless communication standard. In an embodiment a sender of a wireless standard compliant message modulates backchannel data on a wireless standard compliant message. The wireless standard compliant message may be addressed to an IP address of a compliant device. However the compliant message may have no meaning for the addressee. A noncompliant device within wireless range of the compliant message receives the message and demodulates the backchannel information. The noncompliant device this does not require a wireless standard radio to be on in order to receive messages and can operate at very low power.

Abstract: A low power long range transceiver is presented. The transceiver includes: an antenna configured to receive an RF signal; an analog front-end circuit configured to receive the RF signal from the antenna and pre-condition the RF signal by at least one of amplify the RF signal, shift frequency of the RF signal and filter the RF signal; and a demodulator configured to receive the preconditioned signal from the front-end circuit and an assertion trigger signal signifying an end of a predefined time period, where the demodulator, in response to the assertion trigger signal, outputs a data value for a given data bit in the RF signal. A controller is also configured to receive the assertion trigger signal and, in response to the assertion trigger signal, disables at least one component of the transceiver, thereby reducing power consumption.

Abstract: An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (fREF) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (fDCO) to the TDC at least partially based on the first signal input; and generating a phase error output (?ERR) based on the reference signal (fREF) and the PLL output (fDCO), wherein the phase error output (?ERR) is provided as feedback to the controller to control the PLL output (fDCO).

Abstract: In some embodiments, an apparatus includes an integrated circuit such as a system on chip that operates in part from harvested power and that uses information about power harvesting conditions to alter a power-on sequence or boot sequence based on that information. In some embodiments, a method uses information about power harvesting and energy harvesting conditions to alter a power-on sequence or boot sequence.