Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a plurality of memory devices. In some embodiments, a first memory device may transmit a loopback strobe signal based at least in part on a strobe signal for the first memory device. In certain embodiments, a frequency of the loopback strobe signal is a fraction of the frequency of the strobe signal. In some embodiments, the first memory device may transmit a loopback data signal based at least in part on the strobe signal, wherein a frequency of the loopback strobe signal is the fraction of the frequency of the strobe signal.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

Abstract: An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).

Abstract: The described embodiments of the present invention provide an apparatus and method for rapidly programming field programmable devices. A dummy antifuse is provided on the field programmable device for testing prior to actual programming. The current drawn by the device is measured by the programming apparatus until an adequate soaking current is measured while programming the test antifuse. The programming apparatus then records the time required this current level and selects that time as the programming period T.sub.p. This programming time T.sub.p is then used to program the entire device. T.sub.p is now the minimum time required given the process variations of this particular device to adequately program the antifuses which must be blown.

Abstract: A field programmable gate array (10) having a plurality of logic modules (31-35) has a pair of driver circuits (51-52) connected between each logic module (31) and logic module interconnection tracks or lines (12-16, 20-23) (51-52). Each of the drivers (51-52) has an input connected to receive a common output signal from the associated logic module (31). The output from each of the driver circuits (51-52) is selectively connectable to one of the interconnection tracks by a different respective antifuse (27). The output of each driver circuit (51-52) has a current magnitude less than a level that would damage the antifuse (27) but greater than a predetermined level, so that the track capacitances can be charged as rapidly as possible to increase the propagation time of a signal in the array. In one embodiment (10), the respective logic module interconnection lines or tracks 12 to which the pair of antifuses are connected are different logic module interconnection lines (12, 13).

Abstract: A FAMOS memory bit (40) is protected from voltage spike caused by an electrostatic discharge or otherwise by an ESD protection circuit (12). Responsive to a voltage spike on V.sub.pp, the ESD protection circuit (12) couples the drain of the FAMOS memory bit (40) to V.sub.cc or another high capacitance node.

Abstract: A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.

Abstract: A high speed circuit for detecting input or address transitions at a terminal of an integrated circuit logic array. The circuit utilizes N-channel leaker transistors to control the widths of and P-channel transistors to control the risetimes of output pulses and utilizes inverters and OR circuits to sense input or address transitions of both polarities.

Abstract: An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

Abstract: A reference-column circuit for supplying a reference voltage to be used in sensing programming status of read-only-memory cells in a memory array having virtual-ground circuit connections is disclosed. The reference-column circuit includes an adjacent non-programmed memory cell having a common terminal with an identical non-programmed memory cell of prior-art circuitry. The additional memory cell and associated grounding circuit provide a compensating component of reference voltage to the input of a sense amplifier, the compensating component acting to eliminate a source of possible errors in sense amplifier transmission caused by non-programmed adjacent memory cells in the memory array.

Abstract: A discharge circuit for discharging bit lines of an array of semiconductor memory cells in which the array of bit lines are biased from a single bias line. The discharge circuit includes a discharge switch coupled to the bias line for discharging the bit lines and the bias line and a control circuit coupled to the discharge switch operative to turn on the discharge switch in response to the voltage on the bias line rising above a first predetermined level and then to turn off the discharge switch in response to the voltage on the bias line falling below a second predetermined level.

Abstract: A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate.

Abstract: An array of transistor memory cells of a type in which each cell has a transistor, a ground select switch and a sense amplifier coupling switch. A bias voltage line on which there is established a voltage V.sub.BIAS is coupled to each bit line by a bit line transistor whose gate during a read mode is at least about a voltage V.sub.T above V.sub.BIAS. Similarly, the source of each transistor is coupled to the bias voltage line by a source line transistor whose gate is more than about a voltage V.sub.T about V.sub.BIAS. The foregoing arrangement ensures that for every non-selected transistor that transistor's source voltage will be equal to its drain voltage so that all non-selected transistors will be substantially non-conducting.