Patents by Inventor David Dah-Juh Chyan

David Dah-Juh Chyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and mechanism for implementing tessellation-based routing
    Patent number: 7752590
    Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: July 6, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Dah-Juh Chyan, Satish Samuel Raj
  • Method and mechanism for implementing tessellation-based routing
    Patent number: 7694261
    Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Dah-Juh Chyan, Satish Samuel Raj
  • Method and mechanism for implementing tessellation-based routing
    Patent number: 7222322
    Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: May 22, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Dah-Juh Chyan, Satish Samuel Raj