Patents by Inventor David Decrosta

David Decrosta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070187837
    Abstract: A semiconductor structure is provided. In one embodiment, the structure comprises at least one active device located in a substrate and directly under a bond pad. A conductor is located between the bond pad and the substrate. The conductor has a plurality of gaps filled with insulating material. The insulating material is harder than the conductor.
    Type: Application
    Filed: April 19, 2007
    Publication date: August 16, 2007
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty
  • Publication number: 20070184645
    Abstract: A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
    Type: Application
    Filed: April 19, 2007
    Publication date: August 9, 2007
    Applicant: INTERSIL AMERICAS INC.
    Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman Jr., David Decrosta, Robert Lomenick, Chris McCarty
  • Publication number: 20060099823
    Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
    Type: Application
    Filed: December 19, 2005
    Publication date: May 11, 2006
    Applicant: Intersil Americas Inc.
    Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty
  • Publication number: 20050236108
    Abstract: A method of operating a plasma etcher wherein gas is introduced into the etcher at a substantially higher rate than a previous standard rate for a desired etch selectivity, and the throttle valve's open value is set to a substantially greater open value than a previous standard open value for the desired etch selectivity. The method may also include introducing the gas at a lower pressure than the pressure of the previous standard pressure for a desired etch selectivity.
    Type: Application
    Filed: September 17, 2004
    Publication date: October 27, 2005
    Inventor: David DeCrosta
  • Publication number: 20050042853
    Abstract: An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
    Type: Application
    Filed: October 31, 2003
    Publication date: February 24, 2005
    Inventors: John Gasner, Michael Church, Sameer Parab, Paul Bakeman, David Decrosta, Robert Lomenick, Chris McCarty