Patents by Inventor David Desmortreux

David Desmortreux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and wafer with a test structure and method for assessing adhesion of under-bump metallization
    Patent number: 8395399
    Abstract: Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area 22. The semiconductor device includes a first test structure 11 for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas 22. The first test structure includes a pad metal layer portion 24 and a metallization layer portion 18 being in electrical communication with the pad metal layer portion 24 through the common contact area 22. The first test structure 11 further includes connection areas 14, 16 that are electrically connected with each other substantially via the common contact area 22. Upon application of a current between the connection areas 14, 16 a voltage drop occurs that is representative for a voltage drop over the common contact area 22.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: March 12, 2013
    Assignee: NXP B.V.
    Inventors: Lucie Rousseville, Serge Bardy, Philippe Le Duc, David Desmortreux
  • SEMICONDUCTOR DEVICE AND WAFER WITH A TEST STRUCTURE AND METHOD FOR ASSESSING ADHESION OF UNDER-BUMP METALLIZATION
    Publication number: 20100253372
    Abstract: Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area 22. The semiconductor device includes a first test structure 11 for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas 22. The first test structure includes a pad metal layer portion 24 and a metallization layer portion 18 being in electrical communication with the pad metal layer portion 24 through the common contact area 22. The first test structure 11 further includes connection areas 14, 16 that are electrically connected with each other substantially via the common contact area 22. Upon application of a current between the connection areas 14, 16 a voltage drop occurs that is representative for a voltage drop over the common contact area 22.
    Type: Application
    Filed: December 1, 2008
    Publication date: October 7, 2010
    Applicant: NXP B.V.
    Inventors: Lucie Rousseville, Serge Bardy, Philippe Le Duc, David Desmortreux