Patents by Inventor David Dobuzinsky
David Dobuzinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080113507Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.Type: ApplicationFiled: January 15, 2008Publication date: May 15, 2008Applicant: International Business Machines CorporationInventors: David Dobuzinsky, Byeong Kim, Effendi Leobandung, Munir Naeem, Brian Tessier
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Publication number: 20070196963Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.Type: ApplicationFiled: February 21, 2006Publication date: August 23, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Dobuzinsky, Byeong Kim, Effendi Leobandung, Munir Naeem, Brian Tessier
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Publication number: 20070122971Abstract: A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.Type: ApplicationFiled: November 28, 2005Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Dobuzinsky, Herbert Ho, Jack Mandelman, Yoichi Otani
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Publication number: 20060244093Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.Type: ApplicationFiled: June 21, 2006Publication date: November 2, 2006Inventors: Michael Steigerwalt, Mahender Kumar, Herbert Ho, David Dobuzinsky, Johnathan Faltermeier, Denise Pendleton
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Publication number: 20060068596Abstract: A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.Type: ApplicationFiled: September 30, 2004Publication date: March 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Dobuzinsky, Jochen Beintner, Siddhartha Panda
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Publication number: 20050282392Abstract: Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.Type: ApplicationFiled: June 16, 2004Publication date: December 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Steigerwalt, Mahender Kumar, Herbert Ho, David Dobuzinsky, Johnathan Faltermeier, Denise Pendleton
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Patent number: 6960523Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.Type: GrantFiled: April 3, 2003Date of Patent: November 1, 2005Assignees: Infineon Technolgies AG, International Business Machines CorporationInventors: Michael Maldei, Prakash C. Dev, David Dobuzinsky, Johnathan Faltermeier, Thomas S. Rupp, Chienfan Yu, Rajesh Rengarajan, John Benedict, Munir-ud-Din Naeem
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Patent number: 6890815Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.Type: GrantFiled: September 4, 2003Date of Patent: May 10, 2005Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Johnathan Faltermeier, Jeremy Stephens, David Dobuzinsky, Larry Clevenger, Munir D. Naeem, Chienfan Yu, Larry Nesbit, Rama Divakaruni, Michael Maldei
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Patent number: 6869542Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (?20 to 60°).Type: GrantFiled: March 12, 2003Date of Patent: March 22, 2005Assignee: International Business Machines CorporationInventors: Sadanand V. Desphande, David Dobuzinsky, Arpan P. Mahorowala, Tina Wagner, Richard Wise
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Publication number: 20050051839Abstract: A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.Type: ApplicationFiled: September 4, 2003Publication date: March 10, 2005Inventors: Johnathan Faltermeier, Jeremy Stephens, David Dobuzinsky, Larry Clevenger, Munir Naeem, Chienfan Yu, Larry Nesbit, Rama Divakaruni, Michael Maldei
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Publication number: 20050017282Abstract: In the process of forming a trench capacitor, the conductive strap connecting the center electrode of the capacitor with a circuit element in the substrate, such as the pass transistor of a DRAM cell, is separated from the crystalline substrate material by a barrier layer of silicon carbide formed during the process of etching the material within the trench, such as an oxide collar, using a reactive ion etch process with an etchant gas that contains carbon, such as C4F8.Type: ApplicationFiled: July 25, 2003Publication date: January 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Dobuzinsky, Jonathan Faltermeier, Philip Flaitz, Rajarao Jammy, Yuko Ninomiya, Ravikumar Ramachandran, Viraj Sardesai, Yun Wang
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Publication number: 20050014332Abstract: A semiconductor device is fabricated to have improved bitline contact formation. Polysilicon is deposited between gate contacts that connect to transistors of DRAM memory cells. The polysilicon covers the gate contacts and continues to cover the gate contacts during subsequent processing steps. A bitline of, e.g., tungsten, is deposited so that it contacts at least a portion of the polysilicon, thereby providing electrical contact with the DRAM transistors.Type: ApplicationFiled: July 15, 2003Publication date: January 20, 2005Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Michael Maldei, Johnathan Faltermeier, David Dobuzinsky, Prakash Dev, Thomas Rupp
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Patent number: 6806200Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon. In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.Type: GrantFiled: November 8, 2002Date of Patent: October 19, 2004Assignee: International Business Machines CorporationInventors: David Dobuzinsky, Siddhartha Panda, Rolf Weis, Richard Wise
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Publication number: 20040195607Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Michael Maldei, Prakash C. Dev, David Dobuzinsky, Johnathan Faltermeier, Thomas S. Rupp, Chienfan Yu, Rajesh Rengarajan, John Benedict, Munir-ud-Din Naeem
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Publication number: 20040178169Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF2, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (−20 to 60°).Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Applicant: International Business Machines CorporationInventors: Sadanand V. Desphande, David Dobuzinsky, Arpan Mahorowala, Tina Wagner, Richard Wise
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Publication number: 20040092122Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon.Type: ApplicationFiled: November 8, 2002Publication date: May 13, 2004Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp.Inventors: David Dobuzinsky, Siddhartha Panda, Rolf Weis, Richard Wise
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Patent number: 5622596Abstract: Selectivity of SiO.sub.2 to Si.sub.3 N.sub.4 is increased with the additional of silicon rich nitride conformal layer to manufacturing of semiconductor chip. Silicon rich nitride conformal layer may be used in place of or in addition to standard nitride conformal layers in manufacture.Type: GrantFiled: May 8, 1995Date of Patent: April 22, 1997Assignee: International Business Machines CorporationInventors: Michael D. Armacost, David Dobuzinsky, Jeffrey Gambino, Son Nguyen