Patents by Inventor David Doman
David Doman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10068806Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: GrantFiled: February 26, 2018Date of Patent: September 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Publication number: 20180182674Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: ApplicationFiled: February 26, 2018Publication date: June 28, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Publication number: 20180108571Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Patent number: 9947590Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.Type: GrantFiled: October 14, 2016Date of Patent: April 17, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David C. Pritchard, Tuhin Guha Neogi, Scott Luning, David Doman
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Patent number: 9666488Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.Type: GrantFiled: April 11, 2016Date of Patent: May 30, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Tuhin Guha Neogi, David Pritchard, Scott Luning, Guillaume Bouche, David Doman
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Patent number: 9196548Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.Type: GrantFiled: December 28, 2012Date of Patent: November 24, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Srikanth Samavedam, David Doman, Navneet Jain, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8987128Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.Type: GrantFiled: July 30, 2012Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
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Patent number: 8966423Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.Type: GrantFiled: March 11, 2013Date of Patent: February 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
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Publication number: 20140258960Abstract: An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Navneet Jain, Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye
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Publication number: 20140183638Abstract: Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Mahbub RASHED, Srikanth Samavedam, David Doman, Navneet Jain, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8689154Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.Type: GrantFiled: April 13, 2012Date of Patent: April 1, 2014Assignee: GlobalFoundries Inc.Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20140027918Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
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Publication number: 20140001563Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.Type: ApplicationFiled: July 2, 2012Publication date: January 2, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8618607Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.Type: GrantFiled: July 2, 2012Date of Patent: December 31, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20130275935Abstract: An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.Type: ApplicationFiled: April 13, 2012Publication date: October 17, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng, Navneet Jain, Jongwook Kye, Ali Keshavarzi, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20050145111Abstract: A rotary module for implementing a high frequency pressure swing adsorption process comprises a stator and a rotor rotatably coupled to the stator. The stator includes a first stator valve surface, a second stator valve surface, a plurality of first function compartments opening into the first stator valve surface, and a plurality of second function compartments opening into the second stator valve surface. The rotor includes a first rotor valve surface in communication with the first stator valve surface, a second rotor valve surface in communication with the second stator valve surface, and a plurality of flow paths for receiving adsorbent material therein.Type: ApplicationFiled: July 14, 2003Publication date: July 7, 2005Inventors: Bowie Keefer, David Doman, Christopher McLean