Abstract: A method is disclosed for generating pixel risk maps for diagnostic image reconstruction. The method produces uncertainty/variance maps by feeding into a trained encoder a short-scan image acquired from a medical imaging scan to generate latent code statistics including the mean ?y and variance ?y; selecting random samples based on the latent code statistics, z˜N(?y,?y2); feeding the random samples into a trained decoder to generate a pool of reconstructed images; and calculating, for each pixel of the pool of reconstructed images, the pixel mean and variance statistics across the pool of reconstructed images. The risk of each pixel may be calculated using the Stein's Unbiased Risk Estimator on the input density compensated data, that involves calculating the end-to-end divergence of the deep neural network.

Abstract: A method is disclosed for generating pixel risk maps for diagnostic image reconstruction. The method produces uncertainty/variance maps by feeding into a trained encoder a short-scan image acquired from a medical imaging scan to generate latent code statistics including the mean ?y and variance ?y; selecting random samples based on the latent code statistics, z˜N(?y,?y2); feeding the random samples into a trained decoder to generate a pool of reconstructed images; and calculating, for each pixel of the pool of reconstructed images, the pixel mean and variance statistics across the pool of reconstructed images. The risk of each pixel may be calculated using the Stein's Unbiased Risk Estimator on the input density compensated data, that involves calculating the end-to-end divergence of the deep neural network.

Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display. One aspect of the invention is broadly defined as follows: in a computer environment including a software application and an operating system running on a computer, the computer including a graphics card and a video display, the graphics card being operable to render images to the video display. The operating system is operable to: receive draw events; and respond to draw requests from the software application by rendering the draw requests selectively to any of the available hardware layers on the graphics card; whereby the computer environment allows software applications to exploit available hardware layers on the graphics card.

Abstract: The disclosed subject matter includes an apparatus configured to remove a shading effect from an image. The apparatus can include one or more interfaces configured to provide communication with an imaging module that is configured to capture the image, and a processor, in communication with the one or more interfaces, configured to run a module stored in memory. The module is configured to receive the image captured by the imaging module under a first lighting spectrum, receive a per-unit correction mesh for adjusting images captured by the imaging module under a second lighting spectrum, determine a correction mesh for the image captured under the first lighting spectrum based on the per-unit correction mesh for the second lighting spectrum, and operate the correction mesh on the image to remove the shading effect from the image.

Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.

Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display. One aspect of the invention is broadly defined as follows: in a computer environment including a software application and an operating system running on a computer, the computer including a graphics card and a video display, the graphics card being operable to render images to the video display. The operating system is operable to: receive draw events; and respond to draw requests from the software application by rendering the draw requests selectively to any of the available hardware layers on the graphics card; whereby the computer environment allows software applications to exploit available hardware layers on the graphics card.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display.

Abstract: A software application and an operating system may run on a computer, which includes a graphics card and a video display, where the graphics card is operable to render images to the video display, and the operating system includes a universal application programming interface (API) which supports hardware layers on graphics cards. The operating system may be operable to receive draw events via the universal API; determine what hardware layers are available on the graphics card, and what their parameters are; and respond to draw requests from the software application by rendering the draw requests selectively to any of the available hardware layers on the graphics card.

Abstract: A system compositing images from different applications includes a movie clip based application, an image application, and a compositing application that is in communication with the movie clip based application and the image application. The movie clip based application defines one or more movie clip images for display. The image application provides one or more images for display with the one or more movie clip images. The compositing application operates to composite the one or more movie clip images with the one or more images of the image application for viewing on a display.

Abstract: A software application and an operating system may run on a computer, which includes a graphics card and a video display, where the graphics card is operable to render images to the video display, and the operating system includes a universal application programming interface (API) which supports hardware layers on graphics cards. The operating system may be operable to receive draw events via the universal API; determine what hardware layers are available on the graphics card, and what their parameters are; and respond to draw requests from the software application by rendering the draw requests selectively to any of the available hardware layers on the graphics card.

Abstract: A system for compositing images using a multilayer graphics controller includes first and second applications. The first application defines masked display regions to a layer of the multilayer graphics controller using masking criterion. The second application provides an image to a further layer of the multilayer graphics controller for display in the masked region. The image may be a still image, streaming video, Internet image, or any other image type.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display.

Abstract: Fast digital implementations of the second generation curvelet transform for use in data processing are disclosed. One such digital transformation is based on unequally-spaced fast Fourier transforms (USFFT) while another is based on the wrapping of specially selected Fourier samples. Both digital transformations return a table of digital curvelet coefficients indexed by a scale parameter, an orientation parameter, and a spatial location parameter. Both implementations are fast in the sense that they run in about O(n2 log n) flops for n by n Cartesian arrays or about O(N log N) flops for Cartesian arrays of size N=n3; in addition, they are also invertible, with rapid inversion algorithms of about the same complexity.

Abstract: The present invention relates generally to computer graphics, and more specifically to methods of, and systems for, configuring, controlling and accessing multiple hardware graphics layers that are used to compose a single video display.