Abstract: An apparatus comprising high speed ports connected via an integrated high speed serial switch fabric and serializer/deserializer circuits to an internal processing logic, wherein the high speed serial switch fabric is adapted to switch a serial reception signal received by a high speed port to at least one of at least one other high speed port of the apparatus and to the serializer/deserializer circuit of the receiving high speed port.

Abstract: An apparatus comprising high speed ports connected via an integrated high speed serial switch fabric and serializer/deserializer circuits to an internal processing logic, wherein said high speed serial switch fabric is adapted to switch a serial reception signal received by a high speed port to at least one other high speed port of said apparatus and/or to the serializer/deserializer circuit of the receiving high speed port.

Abstract: A system for adding a time stamp to transmission traffic on a wireless network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.

Abstract: A plurality of base station devices are linked together and synchronized to facilitate communication between the respective base station devices and respective downlink subscriber stations. According to one embodiment of the invention, one of the base station devices is designated as a master device, and the other base station devices are designated as slave devices. The respective base station devices are connected to each other by means of a synchronization bus. The master base station device then generates and broadcasts a future time stamp value, which is received by the respective slave base station devices. When the time stamp counter in the master base station device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave base station devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the base station devices are synchronized.

Abstract: A supervisory communications device, such as a base station within a wireless network, monitors and controls communications with a plurality of remote communications devices, such as mobile nodes, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending messages over its downstream channel. The supervisory device also uses the messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: A supervisory communications device, such as a base station within a wireless network, monitors and controls communications with a plurality of remote communications devices, such as mobile nodes, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending messages over its downstream channel. The supervisory device also uses the messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: A plurality of CMTS devices are linked together and synchronized to facilitate communication between the respective CMTS devices and respective downstream cable modems. According to one embodiment of the invention, one of the CMTS devices is designated as a master device, and the other CMTS devices are designated as slave devices. The respective CMTS devices are connected to each other by means of a synchronization bus. The master CMTS device then generates and broadcasts a future time stamp value, which is received by the respective slave CMTS devices. When the time stamp counter in the master CMTS device reaches the transmitted value, a control signal is broadcast over the synchronization bus. The slave CMTS devices then retrieve the time stamp value and reset their respective local time stamp counters to the received value. In this manner, the CMTS devices are synchronized.

Abstract: A method and system for allocating an initial maintenance request (IMR) for an upstream channel in a communications system, wherein the communication system includes a headend and at least one remote device associated with the channel. A first propagation delay from the headend to the remote device having the greatest delay is determined. Likewise, a second propagation delay from the headend to the remote device experiencing the least delay is determined. The IMR is then defined to be shorter than the first propagation delay and at least as long as the difference between the two propagation delays. The starting point of the IMR is established by modifying the clock output of the headend. A modification value is added to the headend clock output. The modification value corresponds to a time interval that can be as long as the propagation delay from the headend to the remote having the shortest delay.

Abstract: A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer jitter lockout circuit inputs the edge pulse and the sampling clock and outputs a data sampling enable signal which never coincides with a data transition.