Abstract: A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

Abstract: A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.

Abstract: A timing generator synchronizes a mobile station internal timing with a base station in a TDMA cellular communication system. A random access memory is used to store an event list comprising a series of events which must be executed periodically at precisely timed intervals. Each event in the event list includes an event time and an event code. The events are stored in the random access memory in the order in which they are to occur. The timing generator of the present invention uses a primary counter, a secondary counter, a synchronizing register, a comparator and a signal generator to control the execution of the event in the event list. The primary counter and secondary counter are both clocked at the same rate. The events are read one at a time from the event list into a compare resister. The event time is compared to the value of the secondary counter. When the event time matches the secondary counter value, the event action is passed to the signal generator which decodes and executes the events.