Abstract: Disclosed are an apparatus and methods for introducing additives into a fluid flow. An additive vessel, with chambers for one or more additives, is attached to a primary flow fixture in a configuration that permits a diversion of part of the primary flow through the additive vessel then back to the outlet of the primary flow fixture. When the apparatus is engaged, a part of the primary flow is diverted to the additive vessel, combines with the additive, and then is re-introduced to the fluid stream, exiting the primary flow fixture.

Abstract: A digital output driver is disclosed. In accordance with some embodiments of the present disclosure, a digital output driver may comprise at least one of an output-source PMOS configured to source current during at least a portion of a low-to-high transition of a digital output, wherein the output-source PMOS is configured to mirror a reference PMOS configured to be driven at its gate by a first amplifier and to be biased by a first reference current, and an output-sink NMOS configured to sink current during at least a portion of a high-to-low transition of the digital output, wherein the output-sink NMOS is configured to mirror a reference NMOS configured to be driven at its gate by a second amplifier and to be biased by a second reference current.

Abstract: A device (110) includes a sensing element (26) having drive nodes (34, 36) and sense nodes (42, 44). Parasitic capacitance (22) is present between drive node (34) and sense node (42). Likewise, parasitic capacitance (24) is present between drive node (36) and sense node (44). When a drive signal (56) is applied between drive nodes (34, 36), a parasitic current (70) between drive and sense nodes (34, 42) and a parasitic current (72) between drive and sense nodes (36,44) is created due to the parasitic capacitances (22, 24). A capacitive network (112) is coupled between the drive node (36) and the sense node (42) to create a correction current (134) through capacitive network (112) that cancels parasitic current (70). Likewise, a capacitive network (114) is coupled between the drive node (34) and the sense node (44) to create a correction current (138) through capacitive network (112) that cancels parasitic current (72).

Abstract: Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Abstract: Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

Abstract: A device (110) includes a sensing element (26) having drive nodes (34, 36) and sense nodes (42, 44). Parasitic capacitance (22) is present between drive node (34) and sense node (42). Likewise, parasitic capacitance (24) is present between drive node (36) and sense node (44). When a drive signal (56) is applied between drive nodes (34, 36), a parasitic current (70) between drive and sense nodes (34, 42) and a parasitic current (72) between drive and sense nodes (36,44) is created due to the parasitic capacitances (22, 24). A capacitive network (112) is coupled between the drive node (36) and the sense node (42) to create a correction current (134) through capacitive network (112) that cancels parasitic current (70). Likewise, a capacitive network (114) is coupled between the drive node (34) and the sense node (44) to create a correction current (138) through capacitive network (112) that cancels parasitic current (72).

Abstract: Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

Abstract: Apparatus are provided for a stacked cascode current source. An apparatus is provided for an electrical device comprising an input node and an output node. A first transistor stack is coupled to the input node. The first transistor stack includes a first transistor and a second transistor. A drain terminal and a gate terminal of the first transistor are coupled to the input node. A drain terminal of the second transistor is coupled to a source terminal of the first transistor and a gate terminal of the second transistor is coupled to the input node. A second transistor stack coupled to the first transistor stack and the output node to create a current mirror for the first transistor stack.

Abstract: Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Abstract: Apparatus are provided for a stacked cascode current source. An apparatus is provided for an electrical device comprising an input node and an output node. A first transistor stack is coupled to the input node. The first transistor stack includes a first transistor and a second transistor. A drain terminal and a gate terminal of the first transistor are coupled to the input node. A drain terminal of the second transistor is coupled to a source terminal of the first transistor and a gate terminal of the second transistor is coupled to the input node. A second transistor stack coupled to the first transistor stack and the output node to create a current mirror for the first transistor stack.

Abstract: A switching circuit includes (a) a bridge circuit (122) with a first output (266) to drive a load (130); and (b) a driver circuit (120) comprising a pair of cascode amplifiers (250, 251) receiving complementary inputs and a bias voltage, wherein the driver circuit (120) is electrically coupled to the bridge circuit (122).

Abstract: A switching circuit includes (a) a bridge circuit (122) with a first output (266) to drive a load (130); and (b) a driver circuit (120) comprising a pair of cascode amplifiers (250, 251) receiving complementary inputs and a bias voltage, wherein the driver circuit (120) is electrically coupled to the bridge circuit (122).

Abstract: A switching regulator provides energy to an inductor-capacitor combination that supply a DC voltage as an output. The presence of a current that can be significantly lower than the typical load current is detected using a pulse signal that provides a measure of the current supplied by the regulator to the inductor. A comparator compares this signal to a reference voltage that is related to the current level to be detected. This reference voltage is adjustable based on the voltage applied by the regulator and the voltage being ultimately supplied as the DC output voltage. The comparator and a capacitor perform an integration function that results in a voltage that ramps upward if the current threshold is being exceeded. When this ramping voltage passes a predetermined level, a signal is provided to indicate that the threshold has been exceeded.

Abstract: A cascode single-ended to differential converter has particular applications for use in communication, e.g. RF circuits. The converter provides higher gain, reduced noise figure and improved output level and linearity over the prior art differential pair converter. The present converter is a transconductor, converting an input voltage to a differential current output signal, i.e., two output signals of different currents, with the difference being linear to the level of voltage. The cascode amplifier output signal is used to produce a signal equal in the amplitude but 180 degrees out of phase with the signal produced by the cascode amplifier.

Abstract: A monolithic microwave oscillator using a negative resistance cell includes a resonator, a negative resistance cell that employs an active device, an output buffer for voltage and current amplification, and a field effect transistor. The negative resistance cell includes a bipolar junction transistor as its active device, with the output buffer circuit coupled to a base of the BJT through the field effect transistor. The combination of the resonator and the negative resistance cell produce a periodic RF microwave signal that is sampled, amplified and buffered by the buffer circuit without degradation.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: An even order term mixer for mixing two ac input signals includes two bipolar junction transistors (each having a base-emitter junction forward bias threshold voltage V.sub.T) with mutually connected collectors and cross-coupled bases and emitters. Each transistor receives a dc emitter bias current I.sub.E and both transistors each receive two single-ended ac input signals V.sub.1 (=.vertline.V.sub.1 .vertline..cos[2.pi.f.sub.1 t]) and V.sub.2 (=.vertline.V.sub.2 .vertline..cos[2.pi.f.sub.2 t]). Each transistor mixes its two ac input signals V.sub.1, V.sub.2 and produces a collector current representing the result thereof. The two collector currents sum at the interconnected collectors and produce across a resistor R.sub.C also connected thereto an ac output voltage V.sub.0 having even order terms and virtually no odd order terms of the mixing products (e.g. sum of and difference between the frequencies) of the two ac input signals.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: A buffer circuit includes an input amplifier connected to receive an input signal and an output amplifier connected provide an output signal. A differential amplifier is connected to also receive the input and output signals and to provide an output related to the difference between the signals to maintain a desired relationship between the input and output signals. The buffer circuit can be configured so that the signal from the differential amplifier is provided either to the input or the output amplifier, and can be accomplished in either bipolar or BICMOS technologies. The combination of the open loop and differential type buffer amplifiers, retains the best features of both, with the excellent speed performance of the open loop circuit as well as the enhanced accuracy of the differential amplifier circuit.

Abstract: A Class A amplifier has a balanced input circuit including first and second input transistors to receive inverting and non-inverting inputs and to provide an output signal on the collector of the first input transistor. First and second load transistors are associated with the input transistors, the bases of the load transistors being connected to the collector of the second input transistor. An output circuit has source and sink output NPN transistors connected to receive the output signal from the first input transistor, and a circuit is provided for dynamically biasing at least one sink output transistor to have a minimum biasing current in a quiescent state, and increased biasing current in a current sink state. The circuit for dynamically biasing the output transistors has a pair of bias NPN transistors with their collector-emitter paths connected in series, and with the base of one connected to receive the output of the first input transistor.