Abstract: A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.

Abstract: A system and method for computational unification of heterogeneous implicit and explicit processing elements which supports the aggregation of any number of such processing elements. The system and method of the present invention supports the generation of a unified executable program through the use of directive statements which are analyzed in conjunction with the semantic structures in the parsed source code to generate appropriate source code targeted to the implicit and explicit processing elements. The computational unification system and method of the present invention further embodies expertise with the particular programming style and idiom of the various processing elements.

Abstract: A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.

Abstract: A system and method for computational unification of heterogeneous implicit and explicit processing elements which supports the aggregation of any number of such processing elements. The system and method of the present invention supports the generation of a unified executable program through the use of directive statements which are analyzed in conjunction with the semantic structures in the parsed source code to generate appropriate source code targeted to the implicit and explicit processing elements. The computational unification system and method of the present invention further embodies expertise with the particular programming style and idiom of the various processing elements.

Abstract: A system and method for computational unification of heterogeneous implicit and explicit processing elements which supports the aggregation of any number of such processing elements. The system and method of the present invention supports the generation of a unified executable program through the use of directive statements which are analyzed in conjunction with the semantic structures in the parsed source code to generate appropriate source code targeted to the implicit and explicit processing elements. The computational unification system and method of the present invention further embodies expertise with the particular programming style and idiom of the various processing elements.

Abstract: A system and method for computational unification of heterogeneous implicit and explicit processing elements which supports the aggregation of any number of such processing elements. The system and method of the present invention supports the generation of a unified executable program through the use of directive statements which are analyzed in conjunction with the semantic structures in the parsed source code to generate appropriate source code targeted to the implicit and explicit processing elements. The computational unification system and method of the present invention further embodies expertise with the particular programming style and idiom of the various processing elements.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.

Abstract: A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.